MIPI-CSI2

Where ?

on the .bus_id ?

Segev

I am not sure the .bus_id control the node number or not. But My understand is it will dynamic assign from 0 like the #16 .That means who comes first who will be assign as first.

Hello,

What do you mean like the #16 ?

Thank you,

Segev

segev

The ‘id = 0’ is the video node could be what you want.

static struct soc_camera_link ov5693_rear_iclink = {
	.bus_id		= 0, /* This must match the .id of tegra_vi01_device */
	.board_info	= &t210ref_ov5693_rear_camera_i2c_device,
	.module_name	= "ov5693_v4l2",
	.i2c_adapter_id	= 6, /* VI2 I2C controller */
	.power		= t210ref_ov5693_power,
	.priv		= &t210ref_ov5693_rear_camera_platform_data,
	.dev_priv	= &t210ref_ov5693_rear_data,


atic struct platform_device t210ref_ov5693_rear_soc_camera_device = {
	.name	= "soc-camera-pdrv",
	.id	= 0,
	.dev	= {
		.platform_data = &ov5693_rear_iclink,
	},

Hello,

Now that it is working in CSI_0, we it to also work on csi_1
on vi2.c , we see
there there is no error status on the CSI_A_STATUS,
but the debug counters show as if the PPB does not receives any packets,

it shows 0000000 when set to show short packet received and long packet receive,

where to debug next ?

we know it works, because in csi_0 it works.

Segev

Hi
Not understand your problem? Did you change the HW to csi_1 and not working? Please post the log.

Hello,

exactly in csi_0 it works, but in csi_1 it does not .

dmesg return CILC_STATUS 0x00000003 which is SOT Multibit Error.

as sanity I removed the FPGA MACH03X, and it gives 0x00000010 as expected.

the FPGHA MACH03X works on CSI_0,

I don’t have i2c

in the

static const struct i2c_device_id ar0330_id = {
{ “ar0330_v4l2”,0 },
{ "ar0330_v4l2_csi_B } ,
{ },
};

So I get the /dev/video0 and /dev/video1
/dev/video0 works,
but /dev/video1 give the CILC Error 0x00000010,

any suggestion how to continue debugging ?

Thank you,

Segev

Hi Segev
What your data lanes? The TK1 CSI_1 only support 1 lane.
If your config is correct you can try the THS_Settle it’s from 1 - 15.
External Media

Are you sure ? On p.1967 in tk1 trm it clearly state that it can use 4 lane for csi a and use 4 lane for csi b and only one lane for csi c,
Can you direct me what it state that csi 1 which I understand is camera b can only support one lane ?

Thank you,

Segev

Hi Segev
TK1 did have 9 lane as TRM, however TK1 camera connector only reserve 4 lane for CSIA and 1 lane for CSIB.

Do you refer to tk1 the processor or tk1 as jetson tk1 board ?

Do you mean tk1 the processor support in csi B only 1 lane ?

Segev

Does your TK1 are customize board not from NVIDIA?
The SOC can support CSIA, CSIB 4 lane and CSIE 1 lane. But jetson TK1 only use 1 lane.

Hello,

we now have additional camera that we want to connect
it is four lane
i see in qv4l

pink screen or green screen
the fps is advancing in 15Hz (suppose to be 30Hz)

but it remain green or pink,

how can i know which format to choose ?

i think it is RAW 12 (color)

i have tried YUVU and many other without success
any suggestions ?

Segev

Hi segen
Is it totally green and pink without any scene? If it doesn’t show up any scene it could be the CSI/VI didn’t get any frame from sensor, please check the dmesg to see if any timeout message then make sure the sensor output single follow the MIPI spec. And what format is depend on the sensor setting you need to check it with sensor vendor.

Thank you,

Segev