Hardware Platform: Jetson AGX Orin
Software Version: JetPack [5.1.2] / L4T [35.4]
Description:
I am integrating a camera system using the MAX96724 deserializer with the Jetson Orin CSI interface.
four sensors->two max96701 and two max96717 → max96724(a single MIPI CSI-2 link) → agx orin
The Configuration:
We have configured the MAX96724 to operate in a mode similar to “Force MIPI Out” (Continuous Clock Mode).
The MAX96724 outputs a continuous high-speed (HS) MIPI clock on the clock lane, even when there is no active video data transmission.
Consequently, the standard MIPI D-PHY LP-11 (Idle state) is not present on the clock lane before the data transmission starts.
The Problem:
We are observing a specific “handshake” failure between the Orin CSI DPHY and the continuous clock source. The behavior is as follows:
Initial State: Power on the system.
Step 1: Run v4l2-ctl --stream-mmap -d /dev/video0.
Result: The command hangs and eventually reports vi timeout. No data is received.
Step 2: Without stopping v4l2-ctl, I manually toggle (disable/enable) the MAX96724 MIPI output clock via I2C.
Result: The stream immediately starts working, and we capture valid video data.
Step 3: Stop the v4l2-ctl stream. Wait for a short period.
Step 4: Try to start the stream again.
Result: It fails with vi timeout again. I must toggle the MAX96724 output again to recover.
The Issue:
I need to verify if the Orin CSI D-PHY receiver can successfully establish a lock and capture data under these conditions.
Hardware Capability: Blind Lock Support: Does the Orin CSI receiver hardware support “Blind Lock” (clk lane entering HS receive mode without detecting the standard LP-11->01->00 sequence)?