what is the mipi register address of jeston TX2.
can anyone help on this.
hello anupam.kumar,
it’s NVCSI to receive MIPI sensor signaling, may I also know what’s your use-case.
please access Tegra X2 Series SoC Technical Reference Manual from download center.
you should check [Table 2: System Address Map] for the base address of NVCSI.
please also check chapter [28.6 MIPI-CSI Registers], for the offsets each MIPI-CSI registers.
thanks
In TX1 for we used to read below mipi status register
CSI_CSI_READONLY_STATUS_0
CSI1_CSI_READONLY_STATUS_0
CSI2_CSI_READONLY_STATUS_0
I am not able to find mipi csi status register in TX2 TRM,can you please tell in 28.6 section which register i can read for mipi status?
hello anupam.kumar,
may I know what’s the status you would like to dig further?
for example,
software driver is using sync-point to talk with low-level camera device. there’re registers, NVCSI_CFG_NVCSI_INCR_SYNCPT_0 you may check for status reports.
there’re error status will be sent to VI, those were reported by NVCSI_STREAM_0_ERROR_STATUS2VI_VC0.
while you had setup sensor and CSI connection, there’ll be NVCSI_STREAM_0_INTR_STATUS to check the error for the streaming.
thanks