Hi,
Trying to encode MIPI signal from an external FPGA device connected to the Jetson TX2 evaluation board on “serial_a” x2 lanes (CLK - pins 7,9 ; D0 - pins 3,5 ; D1 - pins 13,15).
I have configured the device tree and the kernel per [url]https://devtalk.nvidia.com/default/topic/1026772/?comment=5222132[/url].
The format I am trying to sample is 1280x720@60 rgb888 (24bits).
The files that I have modified are attached.
When tracing the debug info it looks like NVidia does not identify the MIPI signal at all (trace is attached, too).
Could someone look into my configuration and direct me in the correctly?
No I meant that looked at the signals on a scope and they looked as data and clock. Though I think that they are missing the LP signal portion.
I just want to verify that my configuration is correct (like video format, number of pixels per line, etc. that I have added all correct values in the correct places).
BTW, I have no I2C bus thus I see failures with accessing the 0x36 device.
hi,
after checking the MIPI signals I am getting from trace the following errors:
CHASEL_SHORT_FRAME, ATOMP_FE - which means that the clock is incorrect though I have set in mode2(Device Tree) the correct clock 74250000.
hi,
The problem was that The function ov5693_write_table was returning an error and thus could not complete the whole frame parsing.
Now I was able to parse a full frame into a file.
Regarding the rgb888 I have added all definitions into extract_pixel_format function in sensor_commonc.c file, are there other places that the rgb888 has to be added?
After applying multiple sensors in the device tree I get the following error “all channel register failed” (in the console or dmesg) what might be causing this failure?
As a result I have no video devices (i.e. /dev/video0, /dev/video1).