MIPI signal from FPGA on Jetson TX2 Evaluation Board

Trying to encode MIPI signal from an external FPGA device connected to the Jetson TX2 evaluation board on “serial_a” x2 lanes (CLK - pins 7,9 ; D0 - pins 3,5 ; D1 - pins 13,15).
I have configured the device tree and the kernel per https://devtalk.nvidia.com/default/topic/1026772/?comment=5222132.
The format I am trying to sample is 1280x720@60 rgb888 (24bits).

The files that I have modified are attached.

When tracing the debug info it looks like NVidia does not identify the MIPI signal at all (trace is attached, too).

Could someone look into my configuration and direct me in the correctly?

Regards, Igal
Trace.txt (6.65 KB)
camera_common.c (21.3 KB)
ov5693.c (38.5 KB)
sensor_common.c (11.4 KB)
tegra186-quill-p3310-1000-a00-00-base.dts.txt (5.67 KB)
camera-dummy.dtsi.txt (9.3 KB)

1 Like

From the trace the VI/CSI didn’t receive any data from MIPI bus. You may need to probe the mipi signal to check.

ShaneCC, hi,

Thanks for the reply.

I have verified the signals and we have data and clocks on the relevant pins as stated in my original mail.

Do I need to check anything else in my configuration?


Hi, you mean the signals are checked OK with mipi spec, right?


No I meant that looked at the signals on a scope and they looked as data and clock. Though I think that they are missing the LP signal portion.

I just want to verify that my configuration is correct (like video format, number of pixels per line, etc. that I have added all correct values in the correct places).

BTW, I have no I2C bus thus I see failures with accessing the 0x36 device.

after checking the MIPI signals I am getting from trace the following errors:
CHASEL_SHORT_FRAME, ATOMP_FE - which means that the clock is incorrect though I have set in mode2(Device Tree) the correct clock 74250000.

How do I verify that this mode is taking affect?

You need make sure the signals are in mipi spec before change configuration.

It’s better to remove all of modes just leave one to debug to avoid confuse.


I have moved to a single mode. Doesn’t work yet.

When I set

v4l2-ctl --all -d /dev/video0

I get that the Pixel Format is AR24 while in my DT it is stated rgb888 :i2c@3180000 / ov5693_c@36 / mode0 /pixel_t = “rgb888”

moreover I can see in the terminal that the pix_clk_hz is equal to 24000 instead of 74250000 as I stated in the DT.

Any ideas?

The Pixel Format shouldn’t not the problem. Below topic have the same symptom. should be the v4l2 framework didn’t have rgb888 so map to AR24.

You saw the 24000 maybe should be the mclk not the pixel clock.

The problem was that The function ov5693_write_table was returning an error and thus could not complete the whole frame parsing.
Now I was able to parse a full frame into a file.
Regarding the rgb888 I have added all definitions into extract_pixel_format function in sensor_commonc.c file, are there other places that the rgb888 has to be added?

Should be no other places need to add.


After applying multiple sensors in the device tree I get the following error “all channel register failed” (in the console or dmesg) what might be causing this failure?
As a result I have no video devices (i.e. /dev/video0, /dev/video1).

An ideas?


It’s could be you DT not implement well. Please have a check the sensor programing guide.

ShaneCCC, hi,

I am sure that the problem is in the DT, though I do not understand what is the problem.


You may need to disable the plug-in manager. Have a check the document to know how to disable it.

ShaneCCC, hi,

I think that I did it, as a single lane does work for me, the problem raises when multiple channels were added.


Then you may need to trace below source to figure what problem for your DT.


Hi igal.kroyter,

Have you clarified the causer and resolved the problem?
Please update the status to move this issue forward.