Hello,
We are trying to bingup our DSI panel which is based on JD9365 LCD driver.
Here is an excerpt from our boot log:
[ 4.171096] tegradc tegradc.0: Display dc.54200000 registered with id=0
[ 4.176844] of_dc_parse_platform_data: DC OR node is connected to /host1x/dsi
[ 4.184044] MJO - Calling internal_panel_select_by_disp_board_id()
[ 4.190216] display board info: id 0x0, fab 0x0
[ 4.194605] MJO - Forcing BOARD_E1549 to be selected
[ 4.199811] MJO - Calling internal_panel_select_by_disp_board_id()
[ 4.205700] display board info: id 0x0, fab 0x0
[ 4.210294] MJO - Forcing BOARD_E1549 to be selected
[ 4.215411] of_dc_parse_platform_data: could not find vrr-settings node
[ 4.221749] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[ 4.228325] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[ 4.235367] tegradc tegradc.0: DT parsed successfully
[ 4.240565] tegradc tegradc.0: DSI: HS clock rate is 283500
[ 4.246473] MJO - Calling dsi_lgd_wxga_7_0_enable()
[ 4.250858] MJO - RST GPIO was specified on DT
[ 4.255098] MJO - About to Initialize the panel
[ 4.588357] ------------[ cut here ]------------
[ 4.590986] WARNING: at drivers/gpio/gpiolib.c:160 gpio_ensure_requested+0x50/0xb0()
[ 4.598692] autorequest GPIO-194
[ 4.601894] Modules linked in:
[ 4.604930] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.96-tegra #1
[ 4.611430] Call trace:
[ 4.613860] [] dump_backtrace+0x0/0xf4
[ 4.619154] —[ end trace af3d5d3c5933a07b ]—
[ 4.848345] ------------[ cut here ]------------
[ 4.850969] WARNING: at drivers/gpio/gpiolib.c:160 gpio_ensure_requested+0x50/0xb0()
[ 4.858679] autorequest GPIO-170
[ 4.861881] Modules linked in:
[ 4.864917] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.10.96-tegra #1
[ 4.872372] Call trace:
[ 4.874798] [] dump_backtrace+0x0/0xf4
[ 4.880084] —[ end trace af3d5d3c5933a07c ]—
[ 5.089594] tegradc tegradc.0: nominal-pclk:67330000 parent:67329786 div:1.0 pclk:67329786 66656700~73389700
[ 5.399787] tegradc tegradc.0: probed
[ 5.481782] fbcon_init: detected unhandled fb_set_par error, error code -22
[ 5.481835] ------------[ cut here ]------------
[ 5.481849] WARNING: at drivers/video/tegra/dc/window.c:320 _tegra_dc_program_windows+0x2cf8/0x6fc8()
[ 5.481853] Modules linked in:
[ 5.481859] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G W 3.10.96-tegra #1
[ 5.481861] Call trace:
[ 5.481867] [] dump_backtrace+0x0/0xf4
[ 5.481870] —[ end trace af3d5d3c5933a07d ]—
[ 5.495889] Console: switching to colour frame buffer device 100x80
[ 5.557322] tegradc tegradc.0: fb registered
Edit 1: Here is the log with our kernel image with board-panel.c and panel-lgd-wxga-7-0.c source code change. We commented out the regulator_get calls.
Edit 2: We are managing to send the display some init commands that we took from a working android driver for the chip we are using (jd9365). However, we have no idea if the frame format for the DSI bus is okay or not. We’ve also reset sequence to make sure reset timing were inside panel spec.
Edit 3: We are managing send some data to the panel, however, an all white bmp appears as green and left hand side of display is black. I’ve updated current boot log and dts file with init-cmd for the panel we are using. Also fbset utilities is crashing with error -22
If we need to create those regulators in our DTS file, than we would like to have some cue for the exact syntax so that regulator can retrieved by the dsi driver.
Any help would be appreciated.
For reference:
Fbset error:
fbcon_init: detected unhandled fb_set_par error, error code -22
Manufacturer panel test code:
/*============================================================================*/
#include "lcd.h"
static LCD_COLOR LCD_Buffer[LCD_XSIZE*LCD_YSIZE];
static GPIO_REG *gpio=GPIO_REG_VA_BASE;
#define LCD_BUF_SIZE (LCD_XSIZE*LCD_YSIZE*sizeof(LCD_COLOR))
#define LCD_BUF_PA_BASE VA2PA((U32)LCD_Buffer)
static void spi_delay(void);
/*============================================================================*/
void Power_IO_init();
#define KEY1 (1 << 5)
#define KEY2 (1 << 6)
#define KEY3 (1 << 7)
void led_on();
void led_off();
unsigned char numint=0;
extern return_main;
extern return_main_addr ;
extern XXW_Main;
U8 CABC=0;
U8 ID_HARD=0;
extern xing[];
extern ASCII_0[],ASCII_1[],ASCII_2[],ASCII_3[],ASCII_4[],ASCII_5[],ASCII_6[],ASCII_7[],
ASCII_8[],ASCII_9[],ASCII_A[],ASCII_B[],ASCII_D[], ASCII_I[],ASCII_V[],
ASCII_C[], ASCII_O[], ASCII_M[],ASCII_MAOHAO[],ASCII_K[],ASCII_N[],ASCII_G[],ASCII_T[],ASCII_E[],ASCII_S[],ASCII_Y[],ASCII_P[],ASCII__[];
extern int lcd_id;
void show_ID(void);
/*============================================================================*/
int Vcom=84; //设置VCOM初值
/*============================================================================*/
#define LCD_POWER_CLR gpio->rGPBDAT = ( gpio->rGPBDAT&(~(1<<6)) )
#define LCD_POWER_SET gpio->rGPBDAT = ( gpio->rGPBDAT|((1<<6)) ) //GPB6
#define LCD_LED_CLR gpio->rGPBDAT = ( gpio->rGPBDAT&(~(1<<0)) )
#define LCD_LED_SET gpio->rGPBDAT = ( gpio->rGPBDAT|((1<<0)) ) //GPB0
/////////////////////////////////////////////////////////////////////////////////////
#define AVDD_CLR gpio->rGPLDAT = ( gpio->rGPLDAT&(~(1<<1)) )
#define AVDD_SET gpio->rGPLDAT = ( gpio->rGPLDAT|((1<<1)) ) //GPL1
#define AVEE_CLR gpio->rGPLDAT = ( gpio->rGPLDAT&(~(1<<2)) )
#define AVEE_SET gpio->rGPLDAT = ( gpio->rGPLDAT|((1<<2)) ) //GPL2
#define VCCIO_CLR gpio->rGPLDAT = ( gpio->rGPLDAT&(~(1<<3)) )
#define VCCIO_SET gpio->rGPLDAT = ( gpio->rGPLDAT|((1<<3)) ) //GPL3
//////////////////////////////////////////////////////////////////////////////////////
/*============================================================================*/
void CPU_SetEPLL(U32 clk_mhz);
void W_C(int data);
void W_D(int data);
void SPI_2825_WrReg(U8 c,U16 value);
void writed16(int data);
void GP_COMMAD_PA(int a);
void SPI_2825_WrCmd(U8 cmd);
void SPI_WriteData(U8 value);
void SPI_3W_SET_PAs(U8 value);
void Write_com(U16 vv);
//void GP_COMMAD_PA(U16 num);
void SPI_3W_SET_Cmd(U8 cmd);
/*============================================================================*/
void pwm_init()
{
int div;
static PWM_REG *pwm=PWM_REG_VA_BASE;
gpio->rGPBCON = 0x00055556;
gpio->rGPBUDP = 0xaaaaaaaa;
// gpio->rGPBDAT = 0x1;
pwm->rTCFG0 =2; // prescaler等于249 f=Pclk(66M)/(249)/3
pwm->rTCFG1 =0x02; //divider等于8，则设置定时器0的时钟频率为25kHz
div=(66000000/2/8)/1000;
pwm->rTCNTB0 = div; //让定时器0每隔5秒中断一次
//pwm->rTCMPB0 =2*div/3; //pwm-> rTCNTB0>>1; // 50% 即占空比 即占空比 控制此参数 可调节背光电流 值越小 电流越小 反之。 最大50000
pwm->rTCMPB0 =1800;//40ma
// pwm->rTCMPB0 =2620;
// pwm->rTCMPB0 =div;
// pwm->rTCMPB0 =
pwm-> rTCON |=(1<<1);//手动更新
pwm-> rTCON =0x0d ; //定时器0开始工作
}
void pwm_init1MA()
{
int div;
static PWM_REG *pwm=PWM_REG_VA_BASE;
gpio->rGPBCON = 0x00055556;
gpio->rGPBUDP = 0xaaaaaaaa;
// gpio->rGPBDAT = 0x1;
pwm->rTCFG0 =2; // prescaler等于249 f=Pclk(66M)/(249)/3
pwm->rTCFG1 =0x02; //divider等于8，则设置定时器0的时钟频率为25kHz
div=(66000000/2/8)/1000;
pwm->rTCNTB0 = div; //让定时器0每隔5秒中断一次
//pwm->rTCMPB0 =2*div/3; //pwm-> rTCNTB0>>1; // 50% 即占空比 即占空比 控制此参数 可调节背光电流 值越小 电流越小 反之。 最大50000
pwm->rTCMPB0 =3180;//40ma
// pwm->rTCMPB0 =2620;
// pwm->rTCMPB0 =div;
// pwm->rTCMPB0 =
pwm-> rTCON |=(1<<1);//手动更新
pwm-> rTCON =0x0d ; //定时器0开始工作
}
void led_on()
{
pwm_init();
//LCD_LED_SET;
}
void led_off()
{
int div;
static PWM_REG *pwm=PWM_REG_VA_BASE;
gpio->rGPBCON = 0x00055555;
gpio->rGPBSEL = 0x0;
gpio->rGPBUDP = 0xaaaaaaaa;
gpio->rGPBDAT = 0;
}
void LCD_POWER_ON()
{
LCD_SPI_Init();LCD_RST_CLR;
LCD_POWER_SET; //打开总5V开关
LCD_RST_CLR;
delay_ms(50); // Delay 10ms // This Delay time is necessary
VCCIO_SET; //打开Vio
delay_ms(20);
AVDD_SET; //打开AVDD
delay_ms(20);
AVEE_SET; //打开AVEE
delay_ms(20);
LCD_RST_SET;delay_ms(50);
//LCD_RST_CLR;delay_ms(50);
//LCD_RST_SET;delay_ms(50);
}
void LCD_POWER_OFF()
{
LCD_REG *lcd =LCD_REG_VA_BASE;
led_off(); //一定要关闭背光脉宽 否则中断激活时可能会失控
DebugPrintf(" in zhonduan\n");
gpio->rGPCCON = 0x55555555;
gpio->rGPCDAT = 0x00000000;
gpio->rGPDCON = 0x55555555;
gpio->rGPDDAT = 0x00000000;
lcd->rWINCON0 &= ~0x01;
lcd->rWINCON1 &= ~0x01;
lcd->rVIDCON0 &= (~3); // 关闭LCD控制器
//////////////////////////////////////////////////////////////////////
W_C(0xB7);
W_D(0x50);//10=TX_CLK 30=PCLK
W_D(0x02);
W_C(0xBD);
W_D(0x00);
W_D(0x00);
///////////////
GP_COMMAD_PA(1);
W_D(0x28);
delay_ms(100);
GP_COMMAD_PA(1);
W_D(0x10);
delay_ms(100);
LCD_RST_CLR;//拉低RST
delay_ms(10);
LCD_SDA_CLR;
LCD_SCL_CLR;
LCD_CS_CLR;
AVEE_CLR; DebugPrintf(" avddclr\n");//关闭AVEE
delay_ms(20);
AVDD_CLR; DebugPrintf("aveeclr \n"); //关闭AVDD
delay_ms(20);
VCCIO_CLR; //关闭VCCIO
delay_ms(20);
LCD_POWER_CLR; //关闭所有电源
}
void eint_isr_power(void)
{
delay_ms(200); //Bltomain();
switch(numint)
{
case 0: { LCD_POWER_OFF(); numint=1; INTR_ClearPend(INT_NUM_EINT0);}break; //中断发生后 关闭背光以及所有电源
case 1: {return_main=1; return_main_addr=(int)&XXW_Main; numint=0;INTR_ClearPend(INT_NUM_EINT0);}break; //再次按下中断 程序重新从MAIN函数开始执行
//INTR_ClearPend(INT_NUM_EINT0);
}
}
static void delay(void)
{
volatile int i;
for(i=0;i<2;i++);
}
/*============================================================================*/
void LCD_Init()
{
LCD_SPI_Init();
//// Reset LCD Driver////
LCD_RST_SET;
delay_ms(10); // Delay 1ms
LCD_RST_CLR;
delay_ms(50); // Delay 10ms // This Delay time is necessary
LCD_RST_SET;
delay_ms(100); // Delay 50 ms
//SSD2828_Initial
W_C(0xb7);
W_D(0x50);//50=TX_CLK 70=PCLK
W_D(0x00); //Configuration Register
W_C(0xb8);
W_D(0x00);
W_D(0x00); //VC(Virtual ChannelID) Control Register
W_C(0xb9);
W_D(0x00);//1=PLL disable
W_D(0x00);
//TX_CLK/MS should be between 5Mhz to100Mhz
W_C(0xBA);//PLL=(TX_CLK/MS)*NS 8228=480M 4428=240M 061E=120M 4214=240M 821E=360M 8219=300M
W_D(0x14);//D7-0=NS(0x01 : NS=1)
W_D(0x42);//D15-14=PLL范围 00=62.5-125 01=126-250 10=251-500 11=501-1000 DB12-8=MS(01:MS=1)
W_C(0xBB);//LP Clock Divider LP clock = 400MHz / LPD / 8 = 240 / 8 / 4 = 7.5MHz
W_D(0x03);//D5-0=LPD=0x1 – Divide by 2
W_D(0x00);
W_C(0xb9);
W_D(0x01);//1=PLL disable
W_D(0x00);
//MIPI lane configuration
W_C(0xDE);//通道数
W_D(0x02);//11=4LANE 10=3LANE 01=2LANE 00=1LANE
W_D(0x00);
W_C(0xc9);
W_D(0x02);
W_D(0x23); //p1: HS-Data-zero p2: HS-Data- prepare --> 8031 issue
// delay_ms(100);
/*============================================================================*/
//LCD driver initialization
W_C(0xB7);
W_D(0x50);//10=TX_CLK 30=PCLK
W_D(0x02);
W_C(0xBD);
W_D(0x00);
W_D(0x00);
/*
//Page0
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x00);
//--- PASSWORD ----//
GP_COMMAD_PA(2);W_D(0xE1);W_D(0x93);
GP_COMMAD_PA(2);W_D(0xE2);W_D(0x65);
GP_COMMAD_PA(2);W_D(0xE3);W_D(0xF8);
GP_COMMAD_PA(2);W_D(0x80);W_D(0x03);
//Page0
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x04);
GP_COMMAD_PA(2);W_D(0x2D);W_D(0x03);
//--- Sequence Ctrl ----//
//GP_COMMAD_PA(2);W_D(0x70);W_D(0x10); //DC0);W_D(DC1 10 20
//GP_COMMAD_PA(2);W_D(0x71);W_D(0x13); //DC2);W_D(DC3 13 13
//GP_COMMAD_PA(2);W_D(0x72);W_D(0x06); //DC7 06 06
//GP_COMMAD_PA(2);W_D(0x75);W_D(0x03); // 03 04
//--- Page1 ----//
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x01);
//Set VCOM
GP_COMMAD_PA(2);W_D(0x00);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x01);W_D(0x8E);//A0
GP_COMMAD_PA(2);W_D(0x03);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x04);W_D(0x8E);//A0
//Set Gamma Power);W_D( VGMP);W_D(VGMN);W_D(VGSP);W_D(VGSN
//GP_COMMAD_PA(2);W_D(0x0A);W_D(0x07);
//GP_COMMAD_PA(2);W_D(0x0C);W_D(0x74);
//Set Gamma Power);W_D( VGMP);W_D(VGMN);W_D(VGSP);W_D(VGSN
GP_COMMAD_PA(2);W_D(0x17);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x18);W_D(0xD8);//D7
GP_COMMAD_PA(2);W_D(0x19);W_D(0x01);//00
GP_COMMAD_PA(2);W_D(0x1A);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x1B);W_D(0xD8);
GP_COMMAD_PA(2);W_D(0x1C);W_D(0x01);//00
//Set Gate Power
GP_COMMAD_PA(2);W_D(0x1F);W_D(0x74); //VGH_REG=17V 6A VGH_REG=15V
GP_COMMAD_PA(2);W_D(0x20);W_D(0x19); //VGL_REG=-8V 23 VGL_REG=-10V
GP_COMMAD_PA(2);W_D(0x21);W_D(0x19); //VGL_REG2=-8V 23 VGL_REG2=-10V
GP_COMMAD_PA(2);W_D(0x22);W_D(0x0E);
//SET RGBCYC
GP_COMMAD_PA(2);W_D(0x37);W_D(0x29); //SS=1);W_D( BGR=1
GP_COMMAD_PA(2);W_D(0x38);W_D(0x05); //JDT=101 Zig-zag
GP_COMMAD_PA(2);W_D(0x39);W_D(0x08); //RGB_N_EQ1);W_D( modify 20140806
GP_COMMAD_PA(2);W_D(0x3A);W_D(0x18); //12 modify 15/05/06 RGB_N_EQ2);W_D( modify 20140806
GP_COMMAD_PA(2);W_D(0x3B);W_D(0x18); //modify 15/05/06
GP_COMMAD_PA(2);W_D(0x3C);W_D(0x72); //78 modify 15/05/06 SET EQ3 for TE_H
GP_COMMAD_PA(2);W_D(0x3D);W_D(0xFF); //SET CHGEN_ON);W_D( modify 20140827
GP_COMMAD_PA(2);W_D(0x3E);W_D(0xFF); //SET CHGEN_OFF);W_D( modify 20140827
GP_COMMAD_PA(2);W_D(0x3F);W_D(0xFF); //SET CHGEN_OFF2);W_D( modify 20140827
//Set TCON
GP_COMMAD_PA(2);W_D(0x40);W_D(0x06); //RSO 04h=720);W_D( 05h=768);W_D( 06h=800
GP_COMMAD_PA(2);W_D(0x41);W_D(0xA0); //LN=640->1280 line
GP_COMMAD_PA(2);W_D(0x43);W_D(0x10); //VFP
GP_COMMAD_PA(2);W_D(0x44);W_D(0x0E); //VBP
GP_COMMAD_PA(2);W_D(0x45);W_D(0x3C); //HBP
//--- power voltage ----//
GP_COMMAD_PA(2);W_D(0x55);W_D(0x01); //DCDCM=0011);W_D( HX PWR_IC
GP_COMMAD_PA(2);W_D(0x56);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x57);W_D(0x64); //65 modify 15/05/06
GP_COMMAD_PA(2);W_D(0x58);W_D(0x0A); //AVDD
GP_COMMAD_PA(2);W_D(0x59);W_D(0x0A); //VCL &AVEE
GP_COMMAD_PA(2);W_D(0x5A);W_D(0x28); //VGH );W_D(15V
GP_COMMAD_PA(2);W_D(0x5B);W_D(0x10); //VGL);W_D(-10V
//--- Gamma ----//
GP_COMMAD_PA(2);W_D(0x5D);W_D(0x7C); //70
GP_COMMAD_PA(2);W_D(0x5E);W_D(0x60); //56
GP_COMMAD_PA(2);W_D(0x5F);W_D(0x4E); //45
GP_COMMAD_PA(2);W_D(0x60);W_D(0x40); //39
GP_COMMAD_PA(2);W_D(0x61);W_D(0x39); //35
GP_COMMAD_PA(2);W_D(0x62);W_D(0x28); //26
GP_COMMAD_PA(2);W_D(0x63);W_D(0x2A); //2A
GP_COMMAD_PA(2);W_D(0x64);W_D(0x11); //14
GP_COMMAD_PA(2);W_D(0x65);W_D(0x27); //2E
GP_COMMAD_PA(2);W_D(0x66);W_D(0x23); //2D
GP_COMMAD_PA(2);W_D(0x67);W_D(0x21); //2D
GP_COMMAD_PA(2);W_D(0x68);W_D(0x3D); //4C
GP_COMMAD_PA(2);W_D(0x69);W_D(0x2B); //3A
GP_COMMAD_PA(2);W_D(0x6A);W_D(0x33); //45
GP_COMMAD_PA(2);W_D(0x6B);W_D(0x26); //38
GP_COMMAD_PA(2);W_D(0x6C);W_D(0x24); //36
GP_COMMAD_PA(2);W_D(0x6D);W_D(0x18); //2B
GP_COMMAD_PA(2);W_D(0x6E);W_D(0x0A); //1C
GP_COMMAD_PA(2);W_D(0x6F);W_D(0x00); //00
GP_COMMAD_PA(2);W_D(0x70);W_D(0x7C); //70
GP_COMMAD_PA(2);W_D(0x71);W_D(0x60); //56
GP_COMMAD_PA(2);W_D(0x72);W_D(0x4E); //45
GP_COMMAD_PA(2);W_D(0x73);W_D(0x40); //39
GP_COMMAD_PA(2);W_D(0x74);W_D(0x39); //35
GP_COMMAD_PA(2);W_D(0x75);W_D(0x29); //26
GP_COMMAD_PA(2);W_D(0x76);W_D(0x2B); //2A
GP_COMMAD_PA(2);W_D(0x77);W_D(0x12); //14
GP_COMMAD_PA(2);W_D(0x78);W_D(0x27); //2E
GP_COMMAD_PA(2);W_D(0x79);W_D(0x24); //2D
GP_COMMAD_PA(2);W_D(0x7A);W_D(0x21); //2D
GP_COMMAD_PA(2);W_D(0x7B);W_D(0x3E); //4C
GP_COMMAD_PA(2);W_D(0x7C);W_D(0x2B); //3A
GP_COMMAD_PA(2);W_D(0x7D);W_D(0x33); //45
GP_COMMAD_PA(2);W_D(0x7E);W_D(0x26); //38
GP_COMMAD_PA(2);W_D(0x7F);W_D(0x24); //36
GP_COMMAD_PA(2);W_D(0x80);W_D(0x19); //2B
GP_COMMAD_PA(2);W_D(0x81);W_D(0x0A); //1C
GP_COMMAD_PA(2);W_D(0x82);W_D(0x00); //00
//Page2);W_D( for GIP
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x02);
//GIP_L Pin mapping
GP_COMMAD_PA(2);W_D(0x00);W_D(0x0E); //L1/CK2BO/CKV10
GP_COMMAD_PA(2);W_D(0x01);W_D(0x06); //L2/CK2O/CKV2
GP_COMMAD_PA(2);W_D(0x02);W_D(0x0C); //L3/CK1BO/CKV8
GP_COMMAD_PA(2);W_D(0x03);W_D(0x04); //L4/CK1O/CKV0
GP_COMMAD_PA(2);W_D(0x04);W_D(0x08); //L5/CK3O/CKV4
GP_COMMAD_PA(2);W_D(0x05);W_D(0x19); //L6/CK3BO/CKV2
GP_COMMAD_PA(2);W_D(0x06);W_D(0x0A); //L7/CK4O/CKV6
GP_COMMAD_PA(2);W_D(0x07);W_D(0x1B); //L8/CK4BO/CKV14
GP_COMMAD_PA(2);W_D(0x08);W_D(0x00); //L9/STVO/STV0
GP_COMMAD_PA(2);W_D(0x09);W_D(0x1D); //L10
GP_COMMAD_PA(2);W_D(0x0A);W_D(0x1F); //L11/VGL
GP_COMMAD_PA(2);W_D(0x0B);W_D(0x1F); //L12/VGL
GP_COMMAD_PA(2);W_D(0x0C);W_D(0x1D); //L13
GP_COMMAD_PA(2);W_D(0x0D);W_D(0x1D); //L14
GP_COMMAD_PA(2);W_D(0x0E);W_D(0x1D); //L15
GP_COMMAD_PA(2);W_D(0x0F);W_D(0x17); //L16/V1_O/FLM1
GP_COMMAD_PA(2);W_D(0x10);W_D(0x37); //L17/V2_O/FLM1_INV
GP_COMMAD_PA(2);W_D(0x11);W_D(0x1D); //L18
GP_COMMAD_PA(2);W_D(0x12);W_D(0x1F); //L19/BW/VGL
GP_COMMAD_PA(2);W_D(0x13);W_D(0x1E); //L20/FW/VGH
GP_COMMAD_PA(2);W_D(0x14);W_D(0x10); //L21/RST_O/ETV0
GP_COMMAD_PA(2);W_D(0x15);W_D(0x1D); //L22
//GIP_R Pin mapping
GP_COMMAD_PA(2);W_D(0x16);W_D(0x0F); //R1/CK2BE/CKV11
GP_COMMAD_PA(2);W_D(0x17);W_D(0x07); //R2/CK2E/CKV3
GP_COMMAD_PA(2);W_D(0x18);W_D(0x0D); //R3/CK1BE/CKV9
GP_COMMAD_PA(2);W_D(0x19);W_D(0x05); //R4/CK1E/CKV1
GP_COMMAD_PA(2);W_D(0x1A);W_D(0x09); //R5/CK3E/CKV5
GP_COMMAD_PA(2);W_D(0x1B);W_D(0x1A); //R6/CK3BE/CKV13
GP_COMMAD_PA(2);W_D(0x1C);W_D(0x0B); //R7/CK4E/CKV7
GP_COMMAD_PA(2);W_D(0x1D);W_D(0x1C); //R8/CK4BE/CKV15
GP_COMMAD_PA(2);W_D(0x1E);W_D(0x01); //R9/STVE/STV1
GP_COMMAD_PA(2);W_D(0x1F);W_D(0x1D); //R10
GP_COMMAD_PA(2);W_D(0x20);W_D(0x1F); //R11/VGL
GP_COMMAD_PA(2);W_D(0x21);W_D(0x1F); //R12/VGL
GP_COMMAD_PA(2);W_D(0x22);W_D(0x1D); //R13
GP_COMMAD_PA(2);W_D(0x23);W_D(0x1D); //R14
GP_COMMAD_PA(2);W_D(0x24);W_D(0x1D); //R15
GP_COMMAD_PA(2);W_D(0x25);W_D(0x18); //R16/V1_E/FLM2
GP_COMMAD_PA(2);W_D(0x26);W_D(0x38); //R17/V2_E/FLM2_INV
GP_COMMAD_PA(2);W_D(0x27);W_D(0x1D); //R18
GP_COMMAD_PA(2);W_D(0x28);W_D(0x1F); //R19/BW/VGL
GP_COMMAD_PA(2);W_D(0x29);W_D(0x1E); //R20/FW/VGH
GP_COMMAD_PA(2);W_D(0x2A);W_D(0x11); //R21/RST_E/ETV1
GP_COMMAD_PA(2);W_D(0x2B);W_D(0x1D); //R22
//GIP_L_GS Pin mapping
GP_COMMAD_PA(2);W_D(0x2C);W_D(0x09); //L1/CK2BO/CKV5
GP_COMMAD_PA(2);W_D(0x2D);W_D(0x1A); //L2/CK2O/CKV13
GP_COMMAD_PA(2);W_D(0x2E);W_D(0x0B); //L3/CK1BO/CKV7
GP_COMMAD_PA(2);W_D(0x2F);W_D(0x1C); //L4/CK1O/CKV15
GP_COMMAD_PA(2);W_D(0x30);W_D(0x0F); //L5/CK3O/CKV11
GP_COMMAD_PA(2);W_D(0x31);W_D(0x07); //L6/CK3BO/CKV3
GP_COMMAD_PA(2);W_D(0x32);W_D(0x0D); //L7/CK4O/CKV9
GP_COMMAD_PA(2);W_D(0x33);W_D(0x05); //L8/CK4BO/CKV1
GP_COMMAD_PA(2);W_D(0x34);W_D(0x11); //L9/STVO/ETV1
GP_COMMAD_PA(2);W_D(0x35);W_D(0x1D); //L10
GP_COMMAD_PA(2);W_D(0x36);W_D(0x1F); //L11/VGL
GP_COMMAD_PA(2);W_D(0x37);W_D(0x1F); //L12/VGL
GP_COMMAD_PA(2);W_D(0x38);W_D(0x1D); //L13
GP_COMMAD_PA(2);W_D(0x39);W_D(0x1D); //L14
GP_COMMAD_PA(2);W_D(0x3A);W_D(0x1D); //L15
GP_COMMAD_PA(2);W_D(0x3B);W_D(0x18); //L16/V1_O/FLM2
GP_COMMAD_PA(2);W_D(0x3C);W_D(0x38); //L17/V2_O/?
GP_COMMAD_PA(2);W_D(0x3D);W_D(0x1D); //L18
GP_COMMAD_PA(2);W_D(0x3E);W_D(0x1E); //L19/BW/VGH
GP_COMMAD_PA(2);W_D(0x3F);W_D(0x1F); //L20/FW/VGL
GP_COMMAD_PA(2);W_D(0x40);W_D(0x01); //L21/RST_O/STV1
GP_COMMAD_PA(2);W_D(0x41);W_D(0x1D); //L22
//GIP_R_GS Pin mapping
GP_COMMAD_PA(2);W_D(0x42);W_D(0x08); //R1/CK2BE/CKV4
GP_COMMAD_PA(2);W_D(0x43);W_D(0x19); //R2/CK2E/CKV12
GP_COMMAD_PA(2);W_D(0x44);W_D(0x0A); //R3/CK1BE/CKV6
GP_COMMAD_PA(2);W_D(0x45);W_D(0x1B); //R4/CK1E/CKV14
GP_COMMAD_PA(2);W_D(0x46);W_D(0x0E); //R5/CK3E/CKV10
GP_COMMAD_PA(2);W_D(0x47);W_D(0x06); //R6/CK3BE/CKV2
GP_COMMAD_PA(2);W_D(0x48);W_D(0x0C); //R7/CK4E/CKV8
GP_COMMAD_PA(2);W_D(0x49);W_D(0x04); //R8/CK4BE/CKV0
GP_COMMAD_PA(2);W_D(0x4A);W_D(0x10); //R9/STVE/ETV0
GP_COMMAD_PA(2);W_D(0x4B);W_D(0x1D); //R10
GP_COMMAD_PA(2);W_D(0x4C);W_D(0x1F); //R11/VGL
GP_COMMAD_PA(2);W_D(0x4D);W_D(0x1F); //R12/VGL
GP_COMMAD_PA(2);W_D(0x4E);W_D(0x1D); //R13
GP_COMMAD_PA(2);W_D(0x4F);W_D(0x1D); //R14
GP_COMMAD_PA(2);W_D(0x50);W_D(0x1D); //R15
GP_COMMAD_PA(2);W_D(0x51);W_D(0x17); //R16/V1_E/FLM1
GP_COMMAD_PA(2);W_D(0x52);W_D(0x37); //R17/V2_E/?
GP_COMMAD_PA(2);W_D(0x53);W_D(0x1D); //R18
GP_COMMAD_PA(2);W_D(0x54);W_D(0x1E); //R19/BW/VGH
GP_COMMAD_PA(2);W_D(0x55);W_D(0x1F); //R20/FW/VGL
GP_COMMAD_PA(2);W_D(0x56);W_D(0x00); //R21/RST_E/STV0
GP_COMMAD_PA(2);W_D(0x57);W_D(0x1D); //R22
//GIP Timing
GP_COMMAD_PA(2);W_D(0x58);W_D(0x10);
GP_COMMAD_PA(2);W_D(0x59);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x5A);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x5B);W_D(0x10);
GP_COMMAD_PA(2);W_D(0x5C);W_D(0x00); //01
GP_COMMAD_PA(2);W_D(0x5D);W_D(0xD0); //50
GP_COMMAD_PA(2);W_D(0x5E);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x5F);W_D(0x02);
GP_COMMAD_PA(2);W_D(0x60);W_D(0x60);
GP_COMMAD_PA(2);W_D(0x61);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x62);W_D(0x02);
GP_COMMAD_PA(2);W_D(0x63);W_D(0x06);
GP_COMMAD_PA(2);W_D(0x64);W_D(0x6A);
GP_COMMAD_PA(2);W_D(0x65);W_D(0x55);
GP_COMMAD_PA(2);W_D(0x66);W_D(0x0F); //2C
GP_COMMAD_PA(2);W_D(0x67);W_D(0xF7); //73
GP_COMMAD_PA(2);W_D(0x68);W_D(0x08); //05
GP_COMMAD_PA(2);W_D(0x69);W_D(0x08);
GP_COMMAD_PA(2);W_D(0x6A);W_D(0x6A); //66_by Max_20151029
GP_COMMAD_PA(2);W_D(0x6B);W_D(0x10); //dummy clk
GP_COMMAD_PA(2);W_D(0x6C);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x6D);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x6E);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x6F);W_D(0x88);
GP_COMMAD_PA(2);W_D(0x70);W_D(0x00); //00
GP_COMMAD_PA(2);W_D(0x71);W_D(0x17); //00
GP_COMMAD_PA(2);W_D(0x72);W_D(0x06);
GP_COMMAD_PA(2);W_D(0x73);W_D(0x7B);
GP_COMMAD_PA(2);W_D(0x74);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x75);W_D(0x80); //80
GP_COMMAD_PA(2);W_D(0x76);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x77);W_D(0x5D); //0D
GP_COMMAD_PA(2);W_D(0x78);W_D(0x18); //18
GP_COMMAD_PA(2);W_D(0x79);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7A);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7B);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7C);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7D);W_D(0x03);
GP_COMMAD_PA(2);W_D(0x7E);W_D(0x7B);
//Page4
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x04);
//GP_COMMAD_PA(2);W_D(0x04);W_D(0x01); //00 modify 15/05/06
GP_COMMAD_PA(2);W_D(0x09);W_D(0x10); // modify 15/05/06
GP_COMMAD_PA(2);W_D(0x0E);W_D(0x38); // modify 15/05/06
//ESD Check & lane number
GP_COMMAD_PA(2);W_D(0x2B);W_D(0x2B);
GP_COMMAD_PA(2);W_D(0x2D);W_D(0x03);
GP_COMMAD_PA(2);W_D(0x2E);W_D(0x44);
//Page0
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x00);
//Watch dog
GP_COMMAD_PA(2);W_D(0xE6);W_D(0x02);
GP_COMMAD_PA(2);W_D(0xE7);W_D(0x06);
*/
//Page0
//Page0
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x00);
//--- PASSWORD ----//
GP_COMMAD_PA(2);W_D(0xE1);W_D(0x93);
GP_COMMAD_PA(2);W_D(0xE2);W_D(0x65);
GP_COMMAD_PA(2);W_D(0xE3);W_D(0xF8);
GP_COMMAD_PA(2);W_D(0x80);W_D(0x02);
//--- Sequence Ctrl ----//
//GP_COMMAD_PA(2);W_D(0x70);W_D(0x10); //DC0);W_D(DC1 10 20
//GP_COMMAD_PA(2);W_D(0x71);W_D(0x13); //DC2);W_D(DC3 13 13
//GP_COMMAD_PA(2);W_D(0x72);W_D(0x06); //DC7 06 06
//GP_COMMAD_PA(2);W_D(0x75);W_D(0x03); // 03 04
//--- Page1 ----//
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x01);
//Set VCOM
GP_COMMAD_PA(2);W_D(0x00);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x01);W_D(0x8E);//A0
GP_COMMAD_PA(2);W_D(0x03);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x04);W_D(0x8E);//A0
//Set Gamma Power);W_D( VGMP);W_D(VGMN);W_D(VGSP);W_D(VGSN
//GP_COMMAD_PA(2);W_D(0x0A);W_D(0x07);
GP_COMMAD_PA(2);W_D(0x0C);W_D(0x74);
//Set Gamma Power);W_D( VGMP);W_D(VGMN);W_D(VGSP);W_D(VGSN
GP_COMMAD_PA(2);W_D(0x17);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x18);W_D(0xD8);//D7
GP_COMMAD_PA(2);W_D(0x19);W_D(0x01);//00
GP_COMMAD_PA(2);W_D(0x1A);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x1B);W_D(0xD8);
GP_COMMAD_PA(2);W_D(0x1C);W_D(0x01);//00
//Set Gate Power
GP_COMMAD_PA(2);W_D(0x1F);W_D(0x74); //VGH_REG=17V 6A VGH_REG=15V
GP_COMMAD_PA(2);W_D(0x20);W_D(0x19); //VGL_REG=-8V 23 VGL_REG=-10V
GP_COMMAD_PA(2);W_D(0x21);W_D(0x19); //VGL_REG2=-8V 23 VGL_REG2=-10V
GP_COMMAD_PA(2);W_D(0x22);W_D(0x0E);
//SET RGBCYC
GP_COMMAD_PA(2);W_D(0x37);W_D(0x29); //SS=1);W_D( BGR=1
GP_COMMAD_PA(2);W_D(0x38);W_D(0x05); //JDT=101 Zig-zag
GP_COMMAD_PA(2);W_D(0x39);W_D(0x08); //RGB_N_EQ1);W_D( modify 20140806
GP_COMMAD_PA(2);W_D(0x3A);W_D(0x18); //12 modify 15/05/06 RGB_N_EQ2);W_D( modify 20140806
GP_COMMAD_PA(2);W_D(0x3B);W_D(0x18); //modify 15/05/06
GP_COMMAD_PA(2);W_D(0x3C);W_D(0x72); //78 modify 15/05/06 SET EQ3 for TE_H
GP_COMMAD_PA(2);W_D(0x3D);W_D(0xFF); //SET CHGEN_ON);W_D( modify 20140827
GP_COMMAD_PA(2);W_D(0x3E);W_D(0xFF); //SET CHGEN_OFF);W_D( modify 20140827
GP_COMMAD_PA(2);W_D(0x3F);W_D(0xFF); //SET CHGEN_OFF2);W_D( modify 20140827
//Set TCON
GP_COMMAD_PA(2);W_D(0x40);W_D(0x06); //RSO 04h=720);W_D( 05h=768);W_D( 06h=800
GP_COMMAD_PA(2);W_D(0x41);W_D(0xA0); //LN=640->1280 line
GP_COMMAD_PA(2);W_D(0x43);W_D(0x10); //VFP
GP_COMMAD_PA(2);W_D(0x44);W_D(0x0E); //VBP
GP_COMMAD_PA(2);W_D(0x45);W_D(0x3C); //HBP
//--- power voltage ----//
GP_COMMAD_PA(2);W_D(0x55);W_D(0x01); //DCDCM=0011);W_D( HX PWR_IC
GP_COMMAD_PA(2);W_D(0x56);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x57);W_D(0x64); //65 modify 15/05/06
GP_COMMAD_PA(2);W_D(0x58);W_D(0x0A); //AVDD
GP_COMMAD_PA(2);W_D(0x59);W_D(0x0A); //VCL &AVEE
GP_COMMAD_PA(2);W_D(0x5A);W_D(0x28); //VGH );W_D(15V
GP_COMMAD_PA(2);W_D(0x5B);W_D(0x10); //VGL);W_D(-10V
//--- Gamma ----//
GP_COMMAD_PA(2);W_D(0x5D);W_D(0x7C); //70
GP_COMMAD_PA(2);W_D(0x5E);W_D(0x60); //56
GP_COMMAD_PA(2);W_D(0x5F);W_D(0x4E); //45
GP_COMMAD_PA(2);W_D(0x60);W_D(0x40); //39
GP_COMMAD_PA(2);W_D(0x61);W_D(0x39); //35
GP_COMMAD_PA(2);W_D(0x62);W_D(0x28); //26
GP_COMMAD_PA(2);W_D(0x63);W_D(0x2A); //2A
GP_COMMAD_PA(2);W_D(0x64);W_D(0x11); //14
GP_COMMAD_PA(2);W_D(0x65);W_D(0x27); //2E
GP_COMMAD_PA(2);W_D(0x66);W_D(0x23); //2D
GP_COMMAD_PA(2);W_D(0x67);W_D(0x21); //2D
GP_COMMAD_PA(2);W_D(0x68);W_D(0x3D); //4C
GP_COMMAD_PA(2);W_D(0x69);W_D(0x2B); //3A
GP_COMMAD_PA(2);W_D(0x6A);W_D(0x33); //45
GP_COMMAD_PA(2);W_D(0x6B);W_D(0x26); //38
GP_COMMAD_PA(2);W_D(0x6C);W_D(0x24); //36
GP_COMMAD_PA(2);W_D(0x6D);W_D(0x18); //2B
GP_COMMAD_PA(2);W_D(0x6E);W_D(0x0A); //1C
GP_COMMAD_PA(2);W_D(0x6F);W_D(0x00); //00
GP_COMMAD_PA(2);W_D(0x70);W_D(0x7C); //70
GP_COMMAD_PA(2);W_D(0x71);W_D(0x60); //56
GP_COMMAD_PA(2);W_D(0x72);W_D(0x4E); //45
GP_COMMAD_PA(2);W_D(0x73);W_D(0x40); //39
GP_COMMAD_PA(2);W_D(0x74);W_D(0x39); //35
GP_COMMAD_PA(2);W_D(0x75);W_D(0x29); //26
GP_COMMAD_PA(2);W_D(0x76);W_D(0x2B); //2A
GP_COMMAD_PA(2);W_D(0x77);W_D(0x12); //14
GP_COMMAD_PA(2);W_D(0x78);W_D(0x27); //2E
GP_COMMAD_PA(2);W_D(0x79);W_D(0x24); //2D
GP_COMMAD_PA(2);W_D(0x7A);W_D(0x21); //2D
GP_COMMAD_PA(2);W_D(0x7B);W_D(0x3E); //4C
GP_COMMAD_PA(2);W_D(0x7C);W_D(0x2B); //3A
GP_COMMAD_PA(2);W_D(0x7D);W_D(0x33); //45
GP_COMMAD_PA(2);W_D(0x7E);W_D(0x26); //38
GP_COMMAD_PA(2);W_D(0x7F);W_D(0x24); //36
GP_COMMAD_PA(2);W_D(0x80);W_D(0x19); //2B
GP_COMMAD_PA(2);W_D(0x81);W_D(0x0A); //1C
GP_COMMAD_PA(2);W_D(0x82);W_D(0x00); //00
//Page2);W_D( for GIP
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x02);
//GIP_L Pin mapping
GP_COMMAD_PA(2);W_D(0x00);W_D(0x0E); //L1/CK2BO/CKV10
GP_COMMAD_PA(2);W_D(0x01);W_D(0x06); //L2/CK2O/CKV2
GP_COMMAD_PA(2);W_D(0x02);W_D(0x0C); //L3/CK1BO/CKV8
GP_COMMAD_PA(2);W_D(0x03);W_D(0x04); //L4/CK1O/CKV0
GP_COMMAD_PA(2);W_D(0x04);W_D(0x08); //L5/CK3O/CKV4
GP_COMMAD_PA(2);W_D(0x05);W_D(0x19); //L6/CK3BO/CKV2
GP_COMMAD_PA(2);W_D(0x06);W_D(0x0A); //L7/CK4O/CKV6
GP_COMMAD_PA(2);W_D(0x07);W_D(0x1B); //L8/CK4BO/CKV14
GP_COMMAD_PA(2);W_D(0x08);W_D(0x00); //L9/STVO/STV0
GP_COMMAD_PA(2);W_D(0x09);W_D(0x1D); //L10
GP_COMMAD_PA(2);W_D(0x0A);W_D(0x1F); //L11/VGL
GP_COMMAD_PA(2);W_D(0x0B);W_D(0x1F); //L12/VGL
GP_COMMAD_PA(2);W_D(0x0C);W_D(0x1D); //L13
GP_COMMAD_PA(2);W_D(0x0D);W_D(0x1D); //L14
GP_COMMAD_PA(2);W_D(0x0E);W_D(0x1D); //L15
GP_COMMAD_PA(2);W_D(0x0F);W_D(0x17); //L16/V1_O/FLM1
GP_COMMAD_PA(2);W_D(0x10);W_D(0x37); //L17/V2_O/FLM1_INV
GP_COMMAD_PA(2);W_D(0x11);W_D(0x1D); //L18
GP_COMMAD_PA(2);W_D(0x12);W_D(0x1F); //L19/BW/VGL
GP_COMMAD_PA(2);W_D(0x13);W_D(0x1E); //L20/FW/VGH
GP_COMMAD_PA(2);W_D(0x14);W_D(0x10); //L21/RST_O/ETV0
GP_COMMAD_PA(2);W_D(0x15);W_D(0x1D); //L22
//GIP_R Pin mapping
GP_COMMAD_PA(2);W_D(0x16);W_D(0x0F); //R1/CK2BE/CKV11
GP_COMMAD_PA(2);W_D(0x17);W_D(0x07); //R2/CK2E/CKV3
GP_COMMAD_PA(2);W_D(0x18);W_D(0x0D); //R3/CK1BE/CKV9
GP_COMMAD_PA(2);W_D(0x19);W_D(0x05); //R4/CK1E/CKV1
GP_COMMAD_PA(2);W_D(0x1A);W_D(0x09); //R5/CK3E/CKV5
GP_COMMAD_PA(2);W_D(0x1B);W_D(0x1A); //R6/CK3BE/CKV13
GP_COMMAD_PA(2);W_D(0x1C);W_D(0x0B); //R7/CK4E/CKV7
GP_COMMAD_PA(2);W_D(0x1D);W_D(0x1C); //R8/CK4BE/CKV15
GP_COMMAD_PA(2);W_D(0x1E);W_D(0x01); //R9/STVE/STV1
GP_COMMAD_PA(2);W_D(0x1F);W_D(0x1D); //R10
GP_COMMAD_PA(2);W_D(0x20);W_D(0x1F); //R11/VGL
GP_COMMAD_PA(2);W_D(0x21);W_D(0x1F); //R12/VGL
GP_COMMAD_PA(2);W_D(0x22);W_D(0x1D); //R13
GP_COMMAD_PA(2);W_D(0x23);W_D(0x1D); //R14
GP_COMMAD_PA(2);W_D(0x24);W_D(0x1D); //R15
GP_COMMAD_PA(2);W_D(0x25);W_D(0x18); //R16/V1_E/FLM2
GP_COMMAD_PA(2);W_D(0x26);W_D(0x38); //R17/V2_E/FLM2_INV
GP_COMMAD_PA(2);W_D(0x27);W_D(0x1D); //R18
GP_COMMAD_PA(2);W_D(0x28);W_D(0x1F); //R19/BW/VGL
GP_COMMAD_PA(2);W_D(0x29);W_D(0x1E); //R20/FW/VGH
GP_COMMAD_PA(2);W_D(0x2A);W_D(0x11); //R21/RST_E/ETV1
GP_COMMAD_PA(2);W_D(0x2B);W_D(0x1D); //R22
//GIP_L_GS Pin mapping
GP_COMMAD_PA(2);W_D(0x2C);W_D(0x09); //L1/CK2BO/CKV5
GP_COMMAD_PA(2);W_D(0x2D);W_D(0x1A); //L2/CK2O/CKV13
GP_COMMAD_PA(2);W_D(0x2E);W_D(0x0B); //L3/CK1BO/CKV7
GP_COMMAD_PA(2);W_D(0x2F);W_D(0x1C); //L4/CK1O/CKV15
GP_COMMAD_PA(2);W_D(0x30);W_D(0x0F); //L5/CK3O/CKV11
GP_COMMAD_PA(2);W_D(0x31);W_D(0x07); //L6/CK3BO/CKV3
GP_COMMAD_PA(2);W_D(0x32);W_D(0x0D); //L7/CK4O/CKV9
GP_COMMAD_PA(2);W_D(0x33);W_D(0x05); //L8/CK4BO/CKV1
GP_COMMAD_PA(2);W_D(0x34);W_D(0x11); //L9/STVO/ETV1
GP_COMMAD_PA(2);W_D(0x35);W_D(0x1D); //L10
GP_COMMAD_PA(2);W_D(0x36);W_D(0x1F); //L11/VGL
GP_COMMAD_PA(2);W_D(0x37);W_D(0x1F); //L12/VGL
GP_COMMAD_PA(2);W_D(0x38);W_D(0x1D); //L13
GP_COMMAD_PA(2);W_D(0x39);W_D(0x1D); //L14
GP_COMMAD_PA(2);W_D(0x3A);W_D(0x1D); //L15
GP_COMMAD_PA(2);W_D(0x3B);W_D(0x18); //L16/V1_O/FLM2
GP_COMMAD_PA(2);W_D(0x3C);W_D(0x38); //L17/V2_O/?
GP_COMMAD_PA(2);W_D(0x3D);W_D(0x1D); //L18
GP_COMMAD_PA(2);W_D(0x3E);W_D(0x1E); //L19/BW/VGH
GP_COMMAD_PA(2);W_D(0x3F);W_D(0x1F); //L20/FW/VGL
GP_COMMAD_PA(2);W_D(0x40);W_D(0x01); //L21/RST_O/STV1
GP_COMMAD_PA(2);W_D(0x41);W_D(0x1D); //L22
//GIP_R_GS Pin mapping
GP_COMMAD_PA(2);W_D(0x42);W_D(0x08); //R1/CK2BE/CKV4
GP_COMMAD_PA(2);W_D(0x43);W_D(0x19); //R2/CK2E/CKV12
GP_COMMAD_PA(2);W_D(0x44);W_D(0x0A); //R3/CK1BE/CKV6
GP_COMMAD_PA(2);W_D(0x45);W_D(0x1B); //R4/CK1E/CKV14
GP_COMMAD_PA(2);W_D(0x46);W_D(0x0E); //R5/CK3E/CKV10
GP_COMMAD_PA(2);W_D(0x47);W_D(0x06); //R6/CK3BE/CKV2
GP_COMMAD_PA(2);W_D(0x48);W_D(0x0C); //R7/CK4E/CKV8
GP_COMMAD_PA(2);W_D(0x49);W_D(0x04); //R8/CK4BE/CKV0
GP_COMMAD_PA(2);W_D(0x4A);W_D(0x10); //R9/STVE/ETV0
GP_COMMAD_PA(2);W_D(0x4B);W_D(0x1D); //R10
GP_COMMAD_PA(2);W_D(0x4C);W_D(0x1F); //R11/VGL
GP_COMMAD_PA(2);W_D(0x4D);W_D(0x1F); //R12/VGL
GP_COMMAD_PA(2);W_D(0x4E);W_D(0x1D); //R13
GP_COMMAD_PA(2);W_D(0x4F);W_D(0x1D); //R14
GP_COMMAD_PA(2);W_D(0x50);W_D(0x1D); //R15
GP_COMMAD_PA(2);W_D(0x51);W_D(0x17); //R16/V1_E/FLM1
GP_COMMAD_PA(2);W_D(0x52);W_D(0x37); //R17/V2_E/?
GP_COMMAD_PA(2);W_D(0x53);W_D(0x1D); //R18
GP_COMMAD_PA(2);W_D(0x54);W_D(0x1E); //R19/BW/VGH
GP_COMMAD_PA(2);W_D(0x55);W_D(0x1F); //R20/FW/VGL
GP_COMMAD_PA(2);W_D(0x56);W_D(0x00); //R21/RST_E/STV0
GP_COMMAD_PA(2);W_D(0x57);W_D(0x1D); //R22
//GIP Timing
GP_COMMAD_PA(2);W_D(0x58);W_D(0x10);
GP_COMMAD_PA(2);W_D(0x59);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x5A);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x5B);W_D(0x10);
GP_COMMAD_PA(2);W_D(0x5C);W_D(0x00); //01
GP_COMMAD_PA(2);W_D(0x5D);W_D(0xD0); //50
GP_COMMAD_PA(2);W_D(0x5E);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x5F);W_D(0x02);
GP_COMMAD_PA(2);W_D(0x60);W_D(0x60);
GP_COMMAD_PA(2);W_D(0x61);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x62);W_D(0x02);
GP_COMMAD_PA(2);W_D(0x63);W_D(0x06);
GP_COMMAD_PA(2);W_D(0x64);W_D(0x6A);
GP_COMMAD_PA(2);W_D(0x65);W_D(0x55);
GP_COMMAD_PA(2);W_D(0x66);W_D(0x0F); //2C
GP_COMMAD_PA(2);W_D(0x67);W_D(0xF7); //73
GP_COMMAD_PA(2);W_D(0x68);W_D(0x08); //05
GP_COMMAD_PA(2);W_D(0x69);W_D(0x08);
GP_COMMAD_PA(2);W_D(0x6A);W_D(0x6A); //66_by Max_20151029
GP_COMMAD_PA(2);W_D(0x6B);W_D(0x10); //dummy clk
GP_COMMAD_PA(2);W_D(0x6C);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x6D);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x6E);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x6F);W_D(0x88);
GP_COMMAD_PA(2);W_D(0x70);W_D(0x00); //00
GP_COMMAD_PA(2);W_D(0x71);W_D(0x17); //00
GP_COMMAD_PA(2);W_D(0x72);W_D(0x06);
GP_COMMAD_PA(2);W_D(0x73);W_D(0x7B);
GP_COMMAD_PA(2);W_D(0x74);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x75);W_D(0x80); //80
GP_COMMAD_PA(2);W_D(0x76);W_D(0x01);
GP_COMMAD_PA(2);W_D(0x77);W_D(0x5D); //0D
GP_COMMAD_PA(2);W_D(0x78);W_D(0x18); //18
GP_COMMAD_PA(2);W_D(0x79);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7A);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7B);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7C);W_D(0x00);
GP_COMMAD_PA(2);W_D(0x7D);W_D(0x03);
GP_COMMAD_PA(2);W_D(0x7E);W_D(0x7B);
//Page4
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x04);
//GP_COMMAD_PA(2);W_D(0x04);W_D(0x01); //00 modify 15/05/06
GP_COMMAD_PA(2);W_D(0x09);W_D(0x10); // modify 15/05/06
GP_COMMAD_PA(2);W_D(0x0E);W_D(0x38); // modify 15/05/06
//ESD Check & lane number
GP_COMMAD_PA(2);W_D(0x2B);W_D(0x2B);
GP_COMMAD_PA(2);W_D(0x2D);W_D(0x03);
GP_COMMAD_PA(2);W_D(0x2E);W_D(0x44);
//Page0
GP_COMMAD_PA(2);W_D(0xE0);W_D(0x00);
//Watch dog
GP_COMMAD_PA(2);W_D(0xE6);W_D(0x02);
GP_COMMAD_PA(2);W_D(0xE7);W_D(0x06);
GP_COMMAD_PA(1);W_D(0x11);delay_ms(100);
GP_COMMAD_PA(1);W_D(0x29);delay_ms(100);
//--- TE----//
//GP_COMMAD_PA(2);W_D(0x35);W_D(0x00);
////////////////////////////////////////////////////////////////////////////////////////////////
W_C(0xb7);
W_D(0x50);
W_D(0x02);
W_C(0xBD);
W_D(0x00);
W_D(0x00);
W_C(0xBC);
W_D(0x00);
W_D(0x00);
//W_C(0xBF);
W_C(0x11); //
//W_D(0x00); //
delay_ms(100);
W_C(0xBC);
W_D(0x00);
W_D(0x00);
//W_C(0xBF);
W_C(0x29); // Display On
delay_ms(200);
//SSD2825_Initial
W_C(0xb7);
W_D(0x50);
W_D(0x00); //Configuration Register
W_C(0xb8);
W_D(0x00);
W_D(0x00); //VC(Virtual ChannelID) Control Register
W_C(0xb9);
W_D(0x00);//1=PLL disable
W_D(0x00);
W_C(0xBA);//PLL=(TX_CLK/MS)*NS 8228=480M 4428=240M 061E=120M 4214=240M 821E=360M 8219=300M 8225=444M 8224=432
W_D(0x33);//D7-0=NS(0x01 : NS=1)2C
W_D(0x82);//D15-14=PLL范围 00=62.5-125 01=126-250 10=251-500 11=501-1000 DB12-8=MS(01:MS=1)
W_C(0xBB);//LP Clock Divider LP clock = 400MHz / LPD / 8 = 480 / 8/ 8 = 7MHz
W_D(0x07);//D5-0=LPD=0x1 – Divide by 2
W_D(0x00);
W_C(0xb9);
W_D(0x01);//1=PLL disable
W_D(0x00);
W_C(0xc9);
W_D(0x02);
W_D(0x23); //p1: HS-Data-zero p2: HS-Data- prepare --> 8031 issue
delay_ms(100);
W_C(0xCA);
W_D(0x01);//CLK Prepare
W_D(0x23);//Clk Zero
W_C(0xCB); //local_write_reg(addr=0xCB,data=0x0510)
W_D(0x10); //Clk Post
W_D(0x05); //Clk Per
W_C(0xCC); //local_write_reg(addr=0xCC,data=0x100A)
W_D(0x05); //HS Trail
W_D(0x10); //Clk Trail
W_C(0xD0);
W_D(0x00);
W_D(0x00);
//RGB interface configuration
W_C(0xB1);
W_D(HSPW);//HSPW 07
W_D(VSPW);//VSPW 05
W_C(0xB2);
W_D(HBPD);//HBPD 0x64=100
W_D(VBPD);//VBPD 8 减小下移
W_C(0xB3);
W_D(HFPD);//HFPD 8
W_D(VFPD);//VFPD 10
W_C(0xB4);//Horizontal active period 720=02D0
W_D(0x20);//013F=319 02D0=720
W_D(0x03);
W_C(0xB5);//Vertical active period 1280=0500
W_D(0x00);//01DF=479 0500=1280
W_D(0x05);
W_C(0xB6);//RGB CLK 16BPP=00 18BPP=01
W_D(0x03);//D7=0 D6=0 D5=0 D1-0=11 – 24bpp
W_D(0x20);//D15=VS D14=HS D13=CLK D12-9=NC D8=0=Video with blanking packet. 00-F0
//MIPI lane configuration
W_C(0xDE);//通道数
W_D(0x02);//11=4LANE 10=3LANE 01=2LANE 00=1LANE
W_D(0x00);
W_C(0xD6);// 05=BGR 04=RGB
W_D(0x05);//D0=0=RGB 1:BGR D1=1=Most significant byte sent first
W_D(0x00);
W_C(0xB7);
W_D(0x4B);
W_D(0x02);
//W_C(0x2C);
//W_C(0x3C);
}
/*==============================初始化2416LCD控制器==============================================*/
int Lcd_Config(void)
{
LCD_REG *lcd =LCD_REG_VA_BASE;
////////////////////////
LCD_Init();
gpio->rMISCCR |= (1<<28); // select LCD controller for TFT lcd controller
gpio->rGPCCON = 0xAAAAAAAA;
gpio->rGPCUDP = 0xAAAAAAAA;
gpio->rGPDCON = 0xAAAAAAAA;
gpio->rGPDUDP = 0xAAAAAAAA;
lcd->rWINCON0 &= ~0x01;
lcd->rWINCON1 &= ~0x01;
lcd->rVIDCON0 &= (~3); // ENVID Off using Per Frame method
#if (CLKSEL_F==0)
//------LCD_CLK = HCLK----//
lcd->rVIDCON0 = (VIDOUT<<22)|(L1_DATA16<<19)|(L0_DATA16<<16)|(PNRMODE<<13)|(CLKVALUP<<12)|(0<<7)|(CLKVAL_F<<6)|(0<<5)|(CLKDIR<<4)|(CLKSEL_F<<2)|(0<<0);
#endif
#if (CLKSEL_F==1)
//------LCD_CLK = EPLL----//
//CPU_SetEPLL(Vclk_MHZ*2);
CPU_SetEPLL(Vclk_MHZ);
lcd->rVIDCON0 = (VIDOUT<<22)|(L1_DATA16<<19)|(L0_DATA16<<16)|(PNRMODE<<13)|(CLKVALUP<<12)|(0<<7)|(CLKVAL_F<<6)|(0<<5)|(CLKDIR<<4)|(CLKSEL_F<<2)|(0<<0); //0HCLK 1EPLL The 2BIT
#endif
lcd->rVIDCON1 = (IVCLK <<7)|(1<<6)|(1<<5)|(0<<4);
lcd->rVIDTCON0 = ((VBPD-1)<<16)|((VFPD-1)<<8)|(VSPW-1);
lcd->rVIDTCON1 = ((HBPD-1)<<16)|((HFPD-1)<<8)|(HSPW-1);
lcd->rVIDTCON2 = ((LCD_YSIZE-1)<<11)|(LCD_XSIZE-1);
#if(LCD_BPP==16)
lcd->rWINCON0 = (BITSWP<<18)|(BYTSWP<<17)|(HAWSWP<<16)|(WINCONx_16WORD_BURST<<9)|(WINCONx_16BPP_565<<2); // 16word burst, 16bpp,
#endif
#if(LCD_BPP==24)
lcd->rWINCON0 = (BITSWP<<18)|(BYTSWP<<17)|(HAWSWP<<16)|(WINCONx_16WORD_BURST<<9)|(WINCONx_24BPP_888<<2); // 16word burst, 24bpp,
#endif
lcd->rVIDOSD0A = (0<<11)|(0);
lcd->rVIDOSD0B = (LCD_XSIZE-1)<<11|(LCD_YSIZE-1);
lcd->rVIDW00ADD0B0 = (U32)LCD_BUFFER_PA_BASE;
lcd->rVIDW00ADD1B0 = (U32)LCD_BUFFER_PA_BASE + LCD_BUF_SIZE;
lcd->rVIDW00ADD2B0 = (0<<13)|(LCD_XSIZE*sizeof(LCD_COLOR));
lcd->rDITHMODE = (1<<5)|(1<<3)|(1<<1)|(0<<0);
//rDITHMODE = 0;
lcd->rWINCON0 |= 0x1;
lcd->rVIDCON0 |= (1<<5)|0x3;
return 1;
}
void LCD_SPI_Init(void)
{
gpio->rGPBCON = 0x00055555;
gpio->rGPBSEL = 0x0;
gpio->rGPBUDP = 0xaaaaaaaa;
// gpio->rGPHCON = 0x55aaaaaa;
//gpio->rGPHUDP = 0xaaaaaaaa;
gpio->rGPGCON = 0x00000000; //设置INT12 13 为输入模式 用于 CABC ID检测
gpio->rGPGUDP = 0x00000000;
Power_IO_init();//控制上电顺序初始化端口
}
U32 stopIndex;
void Key_Init(void)
{
gpio->rGPFCON = 0x03FF;
gpio->rGPFUDP = 0xABFF;
gpio->rGPFDAT = 0xe0;
//
stopIndex = 0;
}
void stop(void)
{
while( (gpio->rGPFDAT)&((KEY3)));
// while(0);
}
void cabc_read(void)
{
/*
if((gpio->rGPGDAT)&0x10)
delay_ms(10);
if((gpio->rGPGDAT)&0x10)
CABC=1;
else
CABC=0;*/
CABC=(gpio->rGPGDAT)&0x10;
CABC=(gpio->rGPGDAT)&0x10;
CABC=(gpio->rGPGDAT)&0x10;
CABC=(gpio->rGPGDAT)&0x10;
CABC=(gpio->rGPGDAT)&0x10;
CABC=(gpio->rGPGDAT)&0x10;
}
void id_hard_read()
{
ID_HARD=(gpio->rGPGDAT)&0x20;
ID_HARD=(gpio->rGPGDAT)&0x20;
ID_HARD=(gpio->rGPGDAT)&0x20;
ID_HARD=(gpio->rGPGDAT)&0x20;
ID_HARD=(gpio->rGPGDAT)&0x20;
ID_HARD=(gpio->rGPGDAT)&0x20;
}
/*============================================================================*/
U16 SPI_READ(void)
{
U8 cmd,rdT;
U16 reValue;
U32 kk;
LCD_CS_CLR;
LCD_SDA_CLR; //Set DC=0, for writing to Command register
LCD_SCL_CLR;
LCD_SCL_SET;
cmd = 0xB0;
LCD_SCL_CLR;
for(kk=0;kk<8;kk++)
{
if((cmd&0x80)==0x80) LCD_SDA_SET;
else LCD_SDA_CLR;
LCD_SCL_SET;
LCD_SCL_CLR;
cmd = cmd<<1;
}
LCD_SDA_CLR; //Set DC=0, for writing to Command register
LCD_SCL_CLR;
LCD_SCL_SET;
cmd = 0xFA;
LCD_SCL_CLR;
for(kk=0;kk<8;kk++)
{
if((cmd&0x80)==0x80) LCD_SDA_SET;
else LCD_SDA_CLR;
LCD_SCL_SET;
LCD_SCL_CLR;
cmd = cmd<<1;
}
rdT=0;
for(kk=0;kk<8;kk++)
{
rdT = rdT<<1;
LCD_SCL_SET;
if((gpio->rGPBDAT)&0x0400) rdT |= 0x01;
LCD_SCL_CLR;
}
reValue = rdT;
//reValue = (reValue<<8)&0xFF00;
rdT=0;
for(kk=0;kk<8;kk++)
{
rdT = rdT<<1;
LCD_SCL_SET;
if((gpio->rGPBDAT)&0x0400) rdT |= 0x01;
LCD_SCL_CLR;
}
reValue += (rdT<<8);
LCD_CS_SET;
return reValue;
}
void Wr_com_data16(U8 c,U16 value)
{
LCD_CS_CLR;
W_C(c);
W_D(value&0xff);
W_D((value>>8)&0xff);
LCD_CS_SET;
}
void SPI_READ_ID(void)
{
int a;
Wr_com_data16(0xd4, 0x00FA);
a=SPI_READ();
if(a==0x2828)
{
DebugPrintf(" \n");
DebugPrintf("The SSD2828 ID: 0x%x ^-^ successful !! \n",a);
DebugPrintf(" \n");
}
else
{
DebugPrintf(" \n");
DebugPrintf("The SSD2828 ID: 0x%x -_-! failing !!!! \n",a);
DebugPrintf(" \n");
}
}
void Write_com(U16 vv)
{
LCD_CS_CLR;
SPI_3W_SET_Cmd(vv&0xff);
}
/*
void GP_COMMAD_PA(U16 num)
{
if(num<3)
{
SPI_2825_WrReg(0xb7, 0x0210);
}
else
{
SPI_2825_WrReg(0xb7, 0x0610);
}
SPI_2825_WrReg(0xbc, num);
Write_com(0x00bd);
SPI_2825_WrReg(0xbe, num);
Write_com(0x00bf);
LCD_CS_SET;
}
*/
void SPI_2825_WrReg(U8 c,U16 value)
{
LCD_CS_CLR;
W_C(c);
W_D(value&0xff);
W_D((value>>8)&0xff);
LCD_CS_SET;
}
void SPI_2825_WrCmd(U8 cmd)
{
U32 kk;
LCD_CS_CLR;
LCD_SDA_SET; //Set DC=0, for writing to Command register
LCD_SCL_CLR;
LCD_SCL_SET;
LCD_SCL_CLR;
for(kk=0;kk<8;kk++)
{
if((cmd&0x80)==0x80) LCD_SDA_SET;
else LCD_SDA_CLR;
LCD_SCL_SET;
LCD_SCL_CLR;
cmd = cmd<<1;
}
LCD_CS_SET;
}
void SPI_WriteData(U8 value)
{
// printf("-%2x",value);
LCD_CS_CLR;
SPI_3W_SET_PAs(value);
LCD_CS_SET;
}
void SPI_3W_SET_Cmd(U8 cmd)
{
U32 kk;
LCD_SDA_CLR; //Set DC=0, for writing to Command register
LCD_SCL_CLR;
LCD_SCL_SET;
// Delay_us(1);
LCD_SCL_CLR;
for(kk=0;kk<8;kk++)
{
if((cmd&0x80)==0x80) LCD_SDA_SET;
else LCD_SDA_CLR;
LCD_SCL_SET;
LCD_SCL_CLR;
cmd = cmd<<1;
}
}
void SPI_3W_SET_PAs(U8 value)
{
U32 kk;
LCD_SDA_SET; //Set DC=1, for writing to Data register
LCD_SCL_CLR;
LCD_SCL_SET;
// Delay_us(1);
LCD_SCL_CLR;
for(kk=0;kk<8;kk++)
{
if((value&0x80)==0x80) LCD_SDA_SET;
else LCD_SDA_CLR;
LCD_SCL_SET;
LCD_SCL_CLR;
value = value<<1;
}
}
void W_C(int data)
{
// RS=0
int i;
LCD_CS_CLR;
spi_delay();
LCD_SDA_CLR;
spi_delay();
LCD_SCL_CLR;
spi_delay();
LCD_SCL_SET;spi_delay();
for(i=0;i<8;i++)
{
if (data & 0x80)
{LCD_SDA_SET;spi_delay();}
else
{LCD_SDA_CLR;spi_delay();}
data<<= 1;
LCD_SCL_CLR;
spi_delay();
LCD_SCL_SET;
spi_delay();
}
LCD_CS_SET;spi_delay();
}
void W_D(int data)
{
//RS=1
int i;
LCD_CS_CLR;
spi_delay();
LCD_SDA_SET;//BIT8=0 COMM
spi_delay();
LCD_SCL_CLR;
spi_delay();
LCD_SCL_SET;spi_delay();
for(i=0;i<8;i++)
{
if (data & 0x80)
{LCD_SDA_SET;spi_delay();}
else
{LCD_SDA_CLR;spi_delay();}
data<<= 1;
LCD_SCL_CLR;
spi_delay();
LCD_SCL_SET;
spi_delay();
}
LCD_CS_SET;spi_delay();
}
void writed16(int data)
{
//RS=1
int i;
LCD_CS_CLR;
spi_delay();
LCD_SDA_SET;//BIT8=0 COMM
spi_delay();
LCD_SCL_CLR;
spi_delay();
LCD_SCL_SET;spi_delay();
for(i=0;i<8;i++)
{
if (data & 0x80)
{ LCD_SDA_SET;spi_delay();}
else
{LCD_SDA_CLR;spi_delay();}
data<<= 1;
LCD_SCL_CLR;
spi_delay();
LCD_SCL_SET;
spi_delay();
}
LCD_CS_SET;spi_delay();
}
void GP_COMMAD_PA(int a)
{
W_C(0xBC);
writed16(a);
writed16(a>>8);
W_C(0xBF);
}
/*============================================================================*/
static void spi_delay(void)
{
volatile int i;
for(i=0;i<10;i++);
}
void show_ID(void)
{
int idh,idl;
/*
GP_COMMAD_PA(6);W_D(0xF0);
W_D(0x55);
W_D(0xAA);
W_D(0x52);
W_D(0x08);
W_D(0x01);
*/
READ_LCD_ID(0xda);//F4=90
//进入高速模式
DebugPrintf(" \n");
DebugPrintf("The LCD ID: 0x%x ^-^ successful !! \n",lcd_id);
DebugPrintf(" \n");
}
display_ID()
{
int a,b,c,d;
a=(Vcom>>12)&0x000f;
b= (Vcom>>8)&0x000f;
c= (Vcom>>4)&0x000f;
d= Vcom&0x000f;
Draw_Text16(50,100,0x00ff0000,0x00000000,xing);
Draw_ASCII (80,200,0x00ff0000,0xffffffff,ASCII_V);
Draw_ASCII (104,200,0x00ff0000,0xffffffff,ASCII_C);
Draw_ASCII (128,200,0x00ff0000,0xffffffff,ASCII_O);
Draw_ASCII (152,200,0x00ff0000,0xffffffff,ASCII_M);
Draw_ASCII (176,200,0x00ff0000,0xffffffff,ASCII_MAOHAO);
Dispaly_ASCII(200,200,0x00ff0000,0xffffffff,a);
Dispaly_ASCII(223,200,0x00ff0000,0xffffffff,b);
Dispaly_ASCII(247,200,0x00ff0000,0xffffffff,c);
Dispaly_ASCII(271,200,0x00ff0000,0xffffffff,d);
//lcd_id=0x00; //清零ID值变量
//W_C(0xB7);
//W_D(0x4B);
//W_D(0x02);
//while(1);
//W_C(0x2C);
//W_C(0x3C);
}
display_CABC_ID()
{
//int a,b,c,d,e,f,g,h;
/*
Draw_ASCII (80,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (104,200,0x000000FF,0xffffffff,ASCII_A);
Draw_ASCII (128,200,0x000000FF,0xffffffff,ASCII_B);
Draw_ASCII (152,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (176,200,0x000000FF,0xffffffff,ASCII_MAOHAO);
if(CABC==0x10)
{
Draw_ASCII (200,200,0x000000FF,0xffffffff,ASCII_O);
Draw_ASCII (224,200,0x000000FF,0xffffffff,ASCII_K);
}
else
{
Draw_ASCII (200,200,0x000000FF,0xffffffff,ASCII_O);
Draw_ASCII (224,200,0x000000FF,0xffffffff,ASCII_K);
}
*/
Draw_ASCII (20,20,0x000000FF,0x00007f00,ASCII_O);
Draw_ASCII (44,20,0x000000FF,0x00007f00,ASCII_T);
Draw_ASCII (68,20,0x000000FF,0x00007f00,ASCII_P);
Draw_ASCII (116,20,0x000000FF,0x00007f00,ASCII_I);
Draw_ASCII (140,20,0x000000FF,0x00007f00,ASCII_D);
//Draw_ASCII (128,200,0x000000FF,0xffffffff,ASCII_B);
//Draw_ASCII (152,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (164,20,0x000000FF,0x00007f00,ASCII_MAOHAO);
//if(lcd_id==0x4000)
//{
Draw_ASCII (188,20,0x000000FF,0x00007f00,ASCII_P);
Draw_ASCII (212,20,0x000000FF,0x00007f00,ASCII_A);
Draw_ASCII (236,20,0x000000FF,0x00007f00,ASCII_S);
Draw_ASCII (260,20,0x000000FF,0x00007f00,ASCII_S);
//}
//else
//{
//Draw_ASCII (200,250,0x000000FF,0xffffffff,ASCII_O);//N
//Draw_ASCII (224,250,0x000000FF,0xffffffff,ASCII_K);//G
//while(1);//死循环
//}
}
display_TE()
{
//int a,b,c,d,e,f,g,h;
/*
Draw_ASCII (80,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (104,200,0x000000FF,0xffffffff,ASCII_A);
Draw_ASCII (128,200,0x000000FF,0xffffffff,ASCII_B);
Draw_ASCII (152,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (176,200,0x000000FF,0xffffffff,ASCII_MAOHAO);
if(CABC==0x10)
{
Draw_ASCII (200,200,0x000000FF,0xffffffff,ASCII_O);
Draw_ASCII (224,200,0x000000FF,0xffffffff,ASCII_K);
}
else
{
Draw_ASCII (200,200,0x000000FF,0xffffffff,ASCII_O);
Draw_ASCII (224,200,0x000000FF,0xffffffff,ASCII_K);
}
*/
Draw_ASCII (20,20,0xFFFFFFFF,0x00000000,ASCII_T);
Draw_ASCII (44,20,0xFFFFFFFF,0x00000000,ASCII_E);
//Draw_ASCII (128,200,0x000000FF,0xffffffff,ASCII_B);
//Draw_ASCII (152,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (88,20,0xFFFFFFFF,0x00000000,ASCII_T);
//if(lcd_id==0x4000)
//{
Draw_ASCII (112,20,0xFFFFFFFF,0x00000000,ASCII_E);
Draw_ASCII (136,20,0xFFFFFFFF,0x00000000,ASCII_S);
Draw_ASCII (164,20,0xFFFFFFFF,0x00000000,ASCII_T);
//}
//else
//{
//Draw_ASCII (200,250,0x000000FF,0xffffffff,ASCII_O);//N
//Draw_ASCII (224,250,0x000000FF,0xffffffff,ASCII_K);//G
//while(1);//死循环
//}
}
display_type()
{
//int a,b,c,d,e,f,g,h;
/*
Draw_ASCII (80,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (104,200,0x000000FF,0xffffffff,ASCII_A);
Draw_ASCII (128,200,0x000000FF,0xffffffff,ASCII_B);
Draw_ASCII (152,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (176,200,0x000000FF,0xffffffff,ASCII_MAOHAO);
if(CABC==0x10)
{
Draw_ASCII (200,200,0x000000FF,0xffffffff,ASCII_O);
Draw_ASCII (224,200,0x000000FF,0xffffffff,ASCII_K);
}
else
{
Draw_ASCII (200,200,0x000000FF,0xffffffff,ASCII_O);
Draw_ASCII (224,200,0x000000FF,0xffffffff,ASCII_K);
}
*/
Draw_ASCII (20,20,0x00000000,0x007F7F7F,ASCII_T);
Draw_ASCII (44,20,0x00000000,0x007F7F7F,ASCII_Y);
//Draw_ASCII (128,200,0x000000FF,0xffffffff,ASCII_B);
//Draw_ASCII (152,200,0x000000FF,0xffffffff,ASCII_C);
Draw_ASCII (68,20,0x00000000,0x007F7F7F,ASCII_P);
Draw_ASCII (92,20,0x00000000,0x007F7F7F,ASCII_E);
Draw_ASCII (116,20,0x00000000,0x007F7F7F,ASCII_MAOHAO);
Draw_ASCII (140,20,0x00000000,0x007F7F7F,ASCII_9);
Draw_ASCII (164,20,0x00000000,0x007F7F7F,ASCII_0);
Draw_ASCII (188,20,0x00000000,0x007F7F7F,ASCII__);
Draw_ASCII (212,20,0x00000000,0x007F7F7F,ASCII_2);
Draw_ASCII (236,20,0x00000000,0x007F7F7F,ASCII_5);
Draw_ASCII (260,20,0x00000000,0x007F7F7F,ASCII_0);
Draw_ASCII (284,20,0x00000000,0x007F7F7F,ASCII_2);
Draw_ASCII (308,20,0x00000000,0x007F7F7F,ASCII_5);
Draw_ASCII (332,20,0x00000000,0x007F7F7F,ASCII__);
Draw_ASCII (356,20,0x00000000,0x007F7F7F,ASCII_5);
Draw_ASCII (380,20,0x00000000,0x007F7F7F,ASCII_4);
Draw_ASCII (404,20,0x00000000,0x007F7F7F,ASCII_7);
Draw_ASCII (428,20,0x00000000,0x007F7F7F,ASCII_8);
Draw_ASCII (452,20,0x00000000,0x007F7F7F,ASCII_B);
//}
//else
//{
//Draw_ASCII (200,250,0x000000FF,0xffffffff,ASCII_O);//N
//Draw_ASCII (224,250,0x000000FF,0xffffffff,ASCII_K);//G
//while(1);//死循环
//}
}
//////////////////////////////中断控制函数//////////////////////////////////
////////////添加中断处理事件//////////////////////
/////////////////////////////////////////////////
/////////////////LCD power 控制////////////////
/////////////////////////////////////////////////
//***********适用搭配OTP烧录MIPI转接板*****//////
void Power_IO_init()
{
gpio->rGPLCON = 0x00055555;//设置GPL 0 1 2 3为输出模式 控制电源开关
}
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
Here is our DC DTS configuration:
dc@54200000 {
compatible = "nvidia,tegra210-dc";
nvidia,dc-or-node = "/host1x/dsi";
power-domains = <0x43>;
reg = <0x0 0x54200000 0x0 0x40000>;
interrupts = <0x0 0x49 0x4>;
iommus = <0x46 0x2 0x46 0xa>;
status = "okay";
avdd_dsi_csi-supply = <0x5c>;
avdd_lcd-supply = <0x78>;
dvdd_lcd-supply = <0x79>;
vdd_lcd_bl_en-supply = <0x7a>;
vdd_lcd_bl-supply = <0x5b>;
vdd_ds_1v8-supply = <0x79>;
avdd_io_edp-supply = <0x7b>;
nvidia,dc-flags = <0x1>;
nvidia,emc-clk-rate = <0x11e1a300>;
nvidia,fb-bpp = <24>;
nvidia,fb-flags = <0x1>;
rgb {
status = "disabled";
};
};
Finally, here is our panel configuration:
dsi {
status = "okay";
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x40000 0x0 0x54400000 0x0 0x40000>;
nvidia,dsi-controller-vs = <0x1>;
orient-display-panel {
status = "okay";
compatible = "lg,wxga-7";
nvidia,dsi-instance = <0x0>;
nvidia,dsi-n-data-lanes = <0x3>;
nvidia,dsi-pixel-format = <0x3>;
nvidia,dsi-refresh-rate = <0x3c>;
//nvidia,dsi-te-polarity-low = <0x1>;
nvidia,dsi-video-data-type = <0x0>;
nvidia,dsi-video-clock-mode = <0x1>;
nvidia,dsi-video-burst-mode = <0x0>; //Note: It can also be 0x01
nvidia,dsi-virtual-channel = <0x0>;
nvidia,dsi-panel-reset = <0x1>; //Note: This was not present at panel-l-wxga-7.dtsi
nvidia,dsi-power-saving-suspend = <0x1>;
nvidia,dsi-lp00-pre-panel-wakeup = <0x0>; //Note: This was not present at panel-l-wxga-7.dtsi
nvidia,dsi-panel-rst-gpio = <0x6a 0xaa 0x0>; // Note: This was not present at panel-l-wxga-7
nvidia,dsi-panel-bl-pwm-gpio = <0x6a 0xa8 0x0>; //Note: This was not present at panel-l-wxga-7
nvidia,dsi-panel-en-gpio = <0x6a 0xa9 0x0>; //Note: This was not present at panel-l-wxga-7
nvidia,dsi-te-gpio = <0x6a 0xc2 0x0>; //Note: This was not present at panel-l-wxga-7
//nvidia,dsi-phy-tlpx = <50>; //Fig 11.7 from datasheet
//nvidia,dsi-phy-hsprepare = <45>; //Fig 11.7 from datasheet
//nvidia,dsi-phy-hsdexit = <100>; //Fig 11.8 from datasheet
// not supported - nvidia,dsi-phy-datzero = <300>; /Fig 11.8 from datasheet
//nvidia,dsi-phy-clkzero = <330>; //Fig 11.8 from datasheet (leaving default ~60ns more)
//nvidia,dsi-phy-clkprepare = <38>; //Fig 11.8 from datasheet
//nvidia,dsi-phy-clktrail = <60>; //Fig 11.8 from datasheet
nvidia,dsi-init-cmd =
<0x0 0x23 0xE0 0x00 0x0>,//Page0
... (Removed some noise)
<0x0 0x23 0xE7 0x06 0x0>,
<0x0 0x15 0x11 0x00>, // Sleep-Out
<0x01 100>,
<0x0 0x15 0x29 0x00>, // DisplayOn
<0x01 100>;
nvidia,dsi-n-init-cmd = <221>;
nvidia,dsi-suspend-cmd = <0x0 0x15 0x10 0x0 0x0>,
<1 160>;
nvidia,dsi-n-suspend-cmd = <2>;
nvidia,dsi-late-resume-cmd = <0x0 0x15 0x11 0x0 0x0>,
<1 100>;
nvidia,dsi-n-late-resume-cmd = <2>;
nvidia,dsi-early-suspend-cmd = <0x0 0x15 0x10 0x0 0x0>,
<1 160>;
nvidia,dsi-n-early-suspend-cmd = <2>;
disp-default-out {
//nvidia,out-rotation = <270>;
//nvidia,out-align = <1>;
//nvidia,out-order = <1>;
nvidia,out-type = <0x2>;
nvidia,out-width = <0x96>;
nvidia,out-height = <0x5E>;
nvidia,out-flags = <0x0>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <1280>;
nvidia,out-yres = <800>;
};
display-timings {
1280x800-24 {
clock-frequency = <67330000>;
hactive = <800>;
vactive = <1280>;
vfront-porch = <16>;
hfront-porch = <40>;
vback-porch = <6>;
hback-porch = <40>;
hsync-len = <20>;
vsync-len = <9>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <1>;
nvidia,h-ref-to-sync = <4>;
nvidia,v-ref-to-sync = <1>;
};
};