Mistake in TX1 Technical Reference Manual

Hi there

I think I have found a problem in the TX1 Technical Reference Manual (TRM) while working with the VI and writing a video input driver.
The sync point values in table 162: Sync Point Conditions (page 2488) appear to be wrong.
I am using TRM DP-072225-001_v1.1p. The last change is dated on May 05 2016 (v1.1).

The first clue is that the order of sync point values is not incrementing consistently (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x06, 0x05, 0x07, …). From my understanding it makes no sense that two different sync point conditions would have the same value.
The second clue is that one condition is duplicate: VI_ISPB_DONE is listed at value 0x0F and 0x1E.

The third clue is that the reserved registers start at 0x21, while the last used register is at 0x1E, so there are two missing registers (presumably the duplicate 0x05, 0x06).

Nvidia, please advise about the correct sync point values for the VI.


If anyone else encounters this problem, here is my solution:

Instead of table 162, use the VI register table: 31.6.1 VI_CFG_VI_INCR_SYNCPT_0. This table so far appears to be correct and complete for VI sync point conditions.

In my opinion table 162 is incorrect and should correspond to aforementioned register table 31.6.1.
Since table 162 is part of the “prose” text describing the VI block (that a reader first encounters when reading about the VI), it would be nice if the contained tables would be correct as well.

Thank you for reporting this kamm, we are working on an update to the documentation.