I’m working on developing custom camera driver and hardware, and thing that isn’t clear in any of the documentation is whether single camera 2-lane CSI-2 is supported. The TRM (yes, I’ve gone through the TRM, the sensor development guide, the V4L user guide, the forums…) lists 1x4 and 2x2 MIPI interfaces, but is it possible to have a configuration with single 2-lane sensor?
The next question is regarding adjusting the settling time register. I’m experiencing a syncpoint timeout with the error register empty, and my camera is definitely streaming out MIPI data on port C.
The V4L User guide says the following:
Sync point timeout without error This means Tegra VI/CSI does not receive any data but no error occurs. Verify that the sensor is powered on and streaming data correctly before debugging the Tegra driver. Change settle time value to see if there if some error shows up. These registers must be configured with the right values to get data from the sensor. cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PHY_CONTROL, 0xA);
Where do you recommend that that register write be added? My intuition is that it should happen somewhere in vi2_probe after err=tegra_camera_init(pdev, &vi2_cam->cam); or possibly in vi2_channel_capture_setup.
I’d also like to clarify what the setting means. The TRM says:
CILA_THS_SETTLE: Settle time for data lane when moving from LP to HS (LP11->LP01- >LP00), this setting determines how many CSICIL clock cycles (102 MHz LP clock cycles) to wait, after LP00, before starting to look at the data. 0xF is an illegal value for this field. 85ns + 6 * UI < (Ths-settle-programmed + 5) * csicil_clk_period < 145ns + 10 * UI
but I could use some help parsing what that actually means. Also, 0x0 is an auto-setup, correct?