More information on Orin NX SPE

Is the Orin NX SPE supported? We can only find information about in the Xavier TRM, the Orin NX TRM has no info

A couple more questions:

  • how are peripherals shared with the Orin NX
  • what’s necessary for application-specific IVC, it looks like only the echo channel works, are there more examples of higher throughput data transfer?

On a very intial test, calling spi_transfer in a loop is resulting in a 44us delay between subsequent transfers. This seems to be because it triggers the DMA code path. Disabling DMA and trying to use PIO doesn’t work

Has the PIO SPI transfer been tested/does it work on the Orin NX SPE?

Hello,

Is the Orin NX SPE supported?

yes. You can take a look at SPE package from BSP 35.4.1. “rt-aux-cpu-demo-fsp/doc/spi-app.md”. Refer to Jetson Orin Nano (Orin NX is almost same as Orin Nano, but with better perf/etc.)

the Orin NX TRM has no info

You can check Orin TRM, and search SPE or AON.

  • how are peripherals shared with the Orin NX

Basically, all modules with AON cluster can be accessed by SPE firmware. But it’s better to check existing demos in rt-aux-cpu-demo-fsp/app/.

  • what’s necessary for application-specific IVC, it looks like only the echo channel works, are there more examples of higher throughput data transfer?

How high throughput you prefer? SPE has very limited perf, and it’s not proper to deal with mass data processing.

Regarding to SPI transfer, both PIO and DMA are supported, but DMA has some issues. You can search forum, and I remembered a few threads were related.
SPI communication of SPE-FW in r35.3.1 may have two bugs - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums
How to send a big array (>256 bytes) by spi communication with DMA mode in spe-fw? - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums

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ChenJian

Can we get access to the R5 with a jtag debugger?

We are finding that with the spi-app.c example, if enabled with ENABLE_SPI_APP=1, causes the entire som to stop booting if we set SPI_TEST_RETRIES to 10.

Are you able to replicate that bug?

The gpio app doesn’t have this issue, we are able to run it throughout the boot sequence

What is an efficient workflow here to rapidly iterate on the SPE firmware?

Is there a way to attach a debugger to it on the Orin NX?

Hello,
Have you ever followed the full instructions in rt-aux-cpu-demo-fsp/doc/spi-app.md, and re-flash the full device?
That demo is verified both internally and externally. It should work.

No official support for JTAG debugger of SPE R5.

br
ChenJian

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