Multi_camera "No cameras available"

I think it doesn’t matter with the format. Even the format is incorrect NVCSI/VI still can receive data but color is incorrect.

@ShaneCCC
I am using fpga to send the data. Is there any demo of the fpga or how can I resolve it?
The signal is RGB888 continuous. 1.5Gb nano
Any important parameter should I set?
The command v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=YUYV --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100
Does pixelformat change to AR24 or what?

You can just set the width and height only to avoid incorrect pixel format.

v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100

For the signal you may need to check the MIPI spec for the timing request.

@ShaneCCC
How can I see if the nvcsi vi are working? Or the status of them?

The cs2_fops.c will print the error status if failed to capture data from MIPI bus.

I know .But it juest print
vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 383.915704] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 383.915719] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 383.915854] vi 54080000.vi: cil_settingtime was autocalculated
[ 383.915873] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 384.117432] video4linux video0: frame start syncpt timeout!0
[ 384.123789] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 384.123806] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 384.123822] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040
[ 384.123914] vi 54080000.vi: cil_settingtime was autocalculated
[ 384.123934] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 384.325408] video4linux video0: frame start syncpt timeout!0
[ 384.331649] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 384.331668] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 384.331684] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040
[ 384.331811] vi 54080000.vi: cil_settingtime was autocalculated
[ 384.331831] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10

But what the ‘X’ in the TEGRA_CSI_CILX_STATUS mean? I found CSI2_CSI_CILB_STATUS_0 CSI2_CSI_CILA_STATUS_0 in the TRM and I don’t know which is it?
The error is that CILB_DATA_LANE0_CTRL_ERR: Control Error. Set when CIL-B detects LP state 01 or 10 followed by a
stop state (LP11) instead of transitioning and the first is CILB_CLK_LANE_CTRL_ERR: Control Error. Set when CIL-B detects incorrect line state sequence on clk
lane. I don’t know what cases the errors.

And I shut down the fpga.The error is the same. I am afraid I have the wrong bind nvcsi and vi. So I want to see which nvcsi and vi is working and the map of them.(csi4, 4lanes, RGB888, 1080P60)

TEGRA_CSI_CIL_STATUS = CSIx_CSI_CIL_A_STATUS_0
TEGRA_CSI_CILX_STATUS = CSIx_CSI_CILA_STATUS_0

I can’t find CSIx_CSI_CIL_A_STATUS_0 or CSIx_CSI_CILA_STATUS_0 in the Tegra_x1_TRM

CSIx were CSI, CSI1,CSI2

Can I know which csi is error ?
csi, csi1 or ci2?

Don’t struggle with which CSI. The driver will read correct port to print it out. You can check the csi2_fops.c to get detail information.

@ShaneCCC
The MIPI still can not capture the image. Which param should I focused?Because the fpga signal to Hisi is ok, But jetosn is failed ~_~

Have a check if the sensor output continuous clocks and it been enable before the CSI/VI start capture.

@ShaneCCC
The fpga signal is always on

Check if can configure the FPGA to output after driver stream_on(), and try configure FPGA to output discontinuous clocks.

The discontinuous FPGA to output after driver stream_on() . But it is the same result.
I set discontinuous_clk = “yes”;.It log TEGRA_CSI_CILX_STATUS 0x00040041
I set discontinuous_clk = “no”; The first time log is TEGRA_CSI_CILX_STATUS 0x00040041, and then keep logging TEGRA_CSI_CILX_STATUS 0x00040041
Here is the FPGA what is the hard ip core can be set

I have use a “HDMI to CSI” chip to connect csi4.I config the chip by a mcu. It can work well on other chips, but the same error on jetson nano. I don’t need to control by i2c.
I want to know the TP is right in the picture? My carrier board is P3450.

I see the post My custom board replace sensor with 2 4-lane sensor(csi2/3 and csi4). how should i edit the dts files? - #59 by y2zwei
Someone said that “for nano, csi2 <-> csiE csi4<->csiC/D”, really?

I have changed the connection to csi0+csi1 4lanes. The report error has changed
[ 515.017305] vi 54080000.vi: Calibrate csi port 0
[ 515.034091] vi 54080000.vi: cil_settingtime was autocalculated
[ 515.034098] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 515.235218] video4linux video0: frame start syncpt timeout!0
[ 515.241607] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 515.241662] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 515.241684] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061
[ 538.386581] video4linux video0: frame start syncpt timeout!0
[ 538.392433] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.392460] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000002
[ 538.392483] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00020020
[ 538.392601] vi 54080000.vi: cil_settingtime was autocalculated
[ 538.392630] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 538.594831] video4linux video0: frame start syncpt timeout!0
[ 538.601087] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.601108] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 538.601125] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061

For the tegra210-camera-rbpcv2-dual-imx219.dtsi one connector is CSIA and another is CSIE

I have changed the connection to csi0+csi1 4lanes. I don’t use the plugin-manager. The report error has changed
[ 515.017305] vi 54080000.vi: Calibrate csi port 0
[ 515.034091] vi 54080000.vi: cil_settingtime was autocalculated
[ 515.034098] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 515.235218] video4linux video0: frame start syncpt timeout!0
[ 515.241607] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 515.241662] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 515.241684] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061
[ 538.386581] video4linux video0: frame start syncpt timeout!0
[ 538.392433] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.392460] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000002
[ 538.392483] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00020020
[ 538.392601] vi 54080000.vi: cil_settingtime was autocalculated
[ 538.392630] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 538.594831] video4linux video0: frame start syncpt timeout!0
[ 538.601087] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.601108] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 538.601125] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061

CILA_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11)
instead of transitioning into the Escape mode or Turn Around mode (LP00).
CILA_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi bit start of
transmission byte error in one of the packets SOT bytes. The packet will be discarded.
what can cause this phenomenon?