Multi_camera "No cameras available"

I have changed the connection to csi0+csi1 4lanes. The report error has changed
[ 515.017305] vi 54080000.vi: Calibrate csi port 0
[ 515.034091] vi 54080000.vi: cil_settingtime was autocalculated
[ 515.034098] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 515.235218] video4linux video0: frame start syncpt timeout!0
[ 515.241607] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 515.241662] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 515.241684] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061
[ 538.386581] video4linux video0: frame start syncpt timeout!0
[ 538.392433] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.392460] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000002
[ 538.392483] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00020020
[ 538.392601] vi 54080000.vi: cil_settingtime was autocalculated
[ 538.392630] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 538.594831] video4linux video0: frame start syncpt timeout!0
[ 538.601087] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.601108] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 538.601125] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061

For the tegra210-camera-rbpcv2-dual-imx219.dtsi one connector is CSIA and another is CSIE

I have changed the connection to csi0+csi1 4lanes. I don’t use the plugin-manager. The report error has changed
[ 515.017305] vi 54080000.vi: Calibrate csi port 0
[ 515.034091] vi 54080000.vi: cil_settingtime was autocalculated
[ 515.034098] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 515.235218] video4linux video0: frame start syncpt timeout!0
[ 515.241607] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 515.241662] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 515.241684] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061
[ 538.386581] video4linux video0: frame start syncpt timeout!0
[ 538.392433] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.392460] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000002
[ 538.392483] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00020020
[ 538.392601] vi 54080000.vi: cil_settingtime was autocalculated
[ 538.392630] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 538.594831] video4linux video0: frame start syncpt timeout!0
[ 538.601087] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 538.601108] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 538.601125] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00060061

CILA_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11)
instead of transitioning into the Escape mode or Turn Around mode (LP00).
CILA_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi bit start of
transmission byte error in one of the packets SOT bytes. The packet will be discarded.
what can cause this phenomenon?

I think devkit only support 2 lanes pin out for CSIA and CSIE, didn’t you using 4 lanes configure?
If yes please configure is as 2 lanes output.

yes,I try to CSIA or CSIA+CSIB, it’s the same
How to change the csi UYVY8_1X16 to YUV8_2X8? Because the HDMI to csi device is YUV8_2X8
entity 4: lt6911uxc 1-002b (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev1
pad0: Source
[fmt:UYVY8_1X16/1920x1080 field:none colorspace:srgb]
→ “nvcsi–1”:0 [ENABLED]

Try modify the csi_pixel_bit_depth = 8
Also you you try RGB888 if the bridge support it like tc358840

I try depth=8 but it’s error
[ 3.768287] lt6911uxc 1-002b: probing lt6911uxc v4l2 sensor at addr 0x2b
[ 3.768374] lt6911uxc 1-002b: mclk absent,assuming sensor driven externally
[ 3.768489] lt6911uxc 1-002b: Unsupported pixel format
[ 3.768493] lt6911uxc 1-002b: Failed to read mode0 image props
[ 3.768498] lt6911uxc 1-002b: Could not initialize sensor properties.
[ 3.768503] lt6911uxc 1-002b: Failed to initialize lt6911uxc
[ 3.768506] lt6911uxc 1-002b: tegra camera driver registration failed
[ 3.768595] lt6911uxc: probe of 1-002b failed with error -22

OK, sorry may need to trace the code to know how to configure it.

How to config?

Looks like there’s no different for UYVY8_1X16 and UYVY8_2X8 both of them config VI as T_U8_Y8__V8_Y8

Your problem maybe signal problem due to “Start of Transmission Multi Bit Error”

 	TEGRA_VIDEO_FORMAT(YUV422, 16, UYVY8_1X16, 2, 1, T_U8_Y8__V8_Y8,
127  				YUV422_8, UYVY, "YUV 4:2:2"),

 	TEGRA_VIDEO_FORMAT(YUV422, 16, UYVY8_2X8, 2, 1, T_U8_Y8__V8_Y8,
137  				YUV422_8, UYVY, "YUV 4:2:2 UYVY"),

I know.
Here is the wave. It seem correct.

Can I skip the error and let nano capture the image?

No, not possible

I see the chip can adjust the Ths-zero and Ths-sync.
Do the parameters engender sot error?
@ShaneCCC

Yes, that control the MIPI timing you may need to check MIPI spec to check if it follow the spec.

The chip can be used with the other soc. The driver don’t be changed. What will affect the sot?

Hi, what’s the bandwidth of your oscilloscope? To check the SOT waveform, please use a scope with enough bandwidth to capture the waveform and compare that to the spec of MIPI. You should be able to do that with MIPI specification.

It’s the sot error.Hardware connection error.

@AlfredNG
Please check For nano B01, csi2 <-> csiE? to review the device tree.