I have seen that the b01 version has pcie1 on the schematic but it is all shown in the rsvd diagram.
1.Is the pcie1 function available after the new version of the document is released?
2.There are only pcie0 on nano-a02. What is the design intention of adding a channel under pcie1?
Hi, Tegra contains a PCIe controller that brings one interface up to four lanes (PCIe0) to the module pins for use on the carrier board. Currently PCIe1 is used on-module for Ethernet.
We saw on the reference design that this pcie1 is rsvd, as shown in my first attached image.
What does this mean?
Reserved for possible change in future, but now it is used for Ethernet in module.