We are currently validating our power up sequence for the custom PCBA carrier board with the Jetson Nano and have a few questions regarding what the state of the peripheral pins should be prior to the Nano fully booting up?
- For USB_VBUS_EN0 (GPIO00) it is called out as Open Drain, 1.8V, however in the USB connection example there is no pull-up shown, but rather it is connected to external open drain. Do we need a 1.8V pull-up or will this affect the power up sequencing requirement of having <0.5V on a GPIO pin during power up?
- Are there any requirements for not having USB2.0 devices connected to the USB0/USB1/USB2 data pins during power up?
- Are there any requirements for not having Gigabit Ethernet connected to the Nano during power up?
- Is there a requirement to keep GPIO08 (Fan TACH) in a specific state during power up?
- UART1 TX/RX does not have this note, (unlike UART0 and UART2): “Buffered on module to keep connected devices from affecting state of the pin during power-on as it is one of the SoC strap pins.” Does this mean that we need to keep the UART1 RX line disconnected from any devices during bootup to prevent this behavior?
- Can the PWR_EN Signal line be run off of 3.3V logic instead of 5V logic