Nano: PWM frequency divisors

We are trying to get a 38kHz carrier on the pwm-2 pin of our Jetson Nano. It is using parent clock “pll_p” which is 408 MHz:

# cat /sys/kernel/debug/clk/pwm/clk_parent 
pll_p
# cat /sys/kernel/debug/clk/pll_p/clk_rate 
408000000

But instead of 38kHz we are seeing 37.4kHz.

I have read this forum post, that says the possible frequencies are clk_rate / (256 * n), where n is an integer between 1 and 2^13.

But those numbers don’t match what we are seeing.

In theory:

clk_rate     n   frequency
===========  ==  =========
408,000,000  38  41,941
408,000,000  39  40,865
408,000,000  40  39,844
408,000,000  41  38,872
408,000,000  42  37,946
408,000,000  43  37,064
408,000,000  44  36,222
408,000,000  45  35,417
408,000,000  46  34,647
408,000,000  47  33,910
408,000,000  48  33,203
408,000,000  49  32,526
408,000,000  50  31,875
408,000,000  51  31,250
408,000,000  52  30,649

What we are seeing:

Requested frequency  Actual frequency
===================  ================
34 kHz               31.21 kHz
36 kHz               37.43 kHz
38 kHz               37.43 kHz
40 kHz               37.43 kHz
42 kHz               46.99 kHz

The actual choices seem to be much more limited than the theory of clk_rate / (256 * n).

Questions:

  1. Do you know why we aren’t getting the theoretical output frequency?
  2. Is there documentation about the PWM hardware?

Hi,
Could you check to other clock parent for a try? The formula is correct and it is a bit strange the clocks are not fit. would suggest try other clock parent.

May also refer to this post:
I want to change the minimum pulse of PWM

It seems that the maximum clock rate is 48MHz (not 408MHz).

This says 408MHz:

# cat /sys/kernel/debug/clk/pll_p/clk_rate 
408000000

But when I use that clock parent, the pwm clock rate says 48MHz:

# cat /sys/kernel/debug/clk/pwm/clk_rate
48000000

For 48MHz, the theoretical calculations do match what we’re seeing.

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