Need help on camera bringup tracing

Hi forum,

I am currently bringing up an FPGA-based bridging with 2-lane MIPI-CSI2 output and received the following dmesg :

[ 2368.737399] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 2368.737569] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[ 2368.738363] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[ 2371.295592] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[ 2371.295840] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 2371.297023] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 2371.297258] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[ 2371.297501] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 2371.297668] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[ 2371.298432] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

and trace :
kworker/0:9-148 [000] .... 543.351963: rtcpu_nvcsi_intr: tstamp:17835048676 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x12000000

Could you help for further debugging, please ?

My system : Jetson Xavier NX +Jetpack-5.1.2

Update :

                       mode0 { //MODE_1920x1080_60FPS
                                mclk_khz = "24000";
                                set_mode_delay_ms = "3000"; /* TEST FPGA */
                                num_lanes = "2";
                                tegra_sinterface = "serial_a";
                                phy_mode = "DPHY";
                                discontinuous_clk = "yes";
                                dpcm_enable = "false";
                                cil_settletime = "0";

                                active_w = "1920";
                                active_h = "1080";
                                pixel_t = "yuv_uyvy16";
                                dynamic_pixel_bit_depth = "16";
                                csi_pixel_bit_depth = "16";
                                readout_orientation = "0";
                                line_length = "2200";
                                inherent_gain = "1";
//                              mclk_multiplier = "2";
                                mclk_multiplier = "10";  /* TEST FPGA */
                                pix_clk_hz = "74250000";

                                gain_factor = "16";
                                framerate_factor = "1000000";
                                exposure_factor = "1000000";
                                min_gain_val = "16"; /* 1.00x */
                                max_gain_val = "170"; /* 10.66x */
                                step_gain_val = "1";
                                default_gain = "16"; /* 1.00x */
                                min_hdr_ratio = "1";
                                max_hdr_ratio = "1";
                                min_framerate = "2000000"; /* 2.0 fps */
//                              max_framerate = "30000000"; /* 30 fps */
                                max_framerate = "60000000"; /* TEST FPGA : 60 fps */
                                step_framerate = "1";
//                              default_framerate = "30000000"; /* 30 fps */
                                default_framerate = "60000000"; /* TEST FPGA : 60 fps */
                                min_exp_time = "13"; /* us */
//                              max_exp_time = "333333"; /* us */
                                max_exp_time = "683709"; /* TEST FPGA */
                                step_exp_time = "1";
                                default_exp_time = "2495"; /* us */

                                embedded_metadata_height = "0";
                        };

Thanks in advance and best regards,
Khang

The PHY_INTR0 tell
intr_dphy_cil_deskew_calib_err_lane0_a and intr_dphy_cil_lane_align_err_a

1 Like

Hi @ShaneCCC,

Thanks for your reply. It turned out that it was an issue of continuous / discontinuous clock mode of the MIPI-CSI2 Tx (FPGA) side.

Best Regards,
Khang