Need help with XDMA Stream for NVIDIA Innova-2 Flex

Infrastructure & Networking Software And Drivers SoC And SmartNIC
1

I successfully wrote data to XDMA Stream on an NVIDIA Innova-2 Flex card, but it took very long and return a -1 error. Can anyone help. This is the info in the dmesg:

[  169.951020] xdma:xdma_xfer_submit: xfer 0x0000000035bb341f,4, s 0x1 timed out, ep 0x4.
[  169.951032] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x00000000d05ca5e0) = 0x1fc08006 (id).
[  169.951036] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x00000000f52e456c) = 0x00000001 (status).
[  169.951041] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x00000000bc38eb94) = 0x00f83e1f (control)
[  169.951045] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x00000000652a07d5) = 0x08c50000 (first_desc_lo)
[  169.951049] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x00000000a4d3480f) = 0x00000001 (first_desc_hi)
[  169.951052] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x0000000091544f7c) = 0x00000000 (first_desc_adjacent).
[  169.951056] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x0000000084de5c0a) = 0x00000000 (completed_desc_count).
[  169.951060] xdma:engine_reg_dump: 0-H2C0-ST: ioread32(0x000000005a435f29) = 0x00f83e1e (interrupt_enable_mask)
[  169.951066] xdma:engine_status_dump: SG engine 0-H2C0-ST status: 0x00000001: BUSY
[  169.951068] xdma:transfer_abort: abort transfer 0x0000000035bb341f, desc 1, engine desc queued 0.
2

This is not enough information. Your issue is likely the result of the interplay between FPGA IP, driver, and software. sudo dmesg | grep -i xdma, the core code in software you are using for communication, and a picture of your Block Design would make this easier.

dma_ip_drivers uses the same dma_to/from_device tools for both Memory-Mapped and Stream IP. I suggest you make the minimal changes to the working demo project to enable AXI-Stream and attempt reading and writing to BRAM Memory using dma_streaming_test.sh.

There is a default 10-second timeout for transactions. Something is blocking them. Either you are attempting to read/write to an incorrect address or the Block you are communicating with is still in Reset. Are you reading or writing to the correct read or write address using the correct read or write device? What are you attempting to communicate with and what is its reset connected to?

Check out Answer Records 65062 - PCI Express Address Mapping and 71435 - XDMA Driver and IP Debug Guide. A very good resource for PCIe which is focused on 7-Series FPGAs is fpgaemu.

3

I have just fixed the block. There is no error now, but it always returns 0 when I read the xdma0_c2h_0. Here is the block design. It is just a multiply function for float numbers:

Screenshot from 2023-07-25 06-35-20
Screenshot from 2023-07-25 06-35-20858×331 24.9 KB

4

This is not the best forum for general FPGA questions. Let’s take this to Xilinx Support.