Netlist of connections between Jetson AGX SoC and module pins


I am requesting a netlist of the connections between the Jetson AGX Xavier SoC and the CVM connector pins. This is currently needed to use the provided BSDL files for boundary scan testing. Essentially the netlist would serve as a “decoder ring” so that boundary scan testing software can trace each CVM pin to a SoC pin in the BSDL.

If I cannot obtain this netlist, my only option is to:

  1. Use the pinmux config template to manually swap each SoC ball name for a CVM Pin name
  2. Change any unconnected pins between SoC and CVM to internal boundary scan cell so it gets ignored in testing

My concern with manually putting together my own BSDL is it is not Nvidia provided and therefore more susceptible to error. It would also be quite a lot of work and Nvidia likely has the means to do this much easier, faster, and accurately.

Please let me know if we can resolve this issue.

We are checking this internally, will update if any result.

Hi, it has been awhile since the initial post. I’m assuming a netlist would be posted if it were created, but what resulted from the internal discussion? Are there plans to provide this?

Not yet.