New design w/ TK1 - Unable to recognize TK1 as USB Device to program bootloader

Hello,
I’m attempting to use Flash.sh (nvflash) to program the bootloader onto a custom TK1 design, I believe I have the TK1 powered to the correct state, but I’m never able to detect the TK1 as a USB Device either when running NVFlash, or with “lsusb”. Here is the command that I am running:
sudo ./flash.sh /bootloader/ardbeg/uboot.bin jetson-tk1 mmcblk0p1
USB device not found
If I connect the TK1 Dev Card and run the same command, I’m able to detect the TK1 as a USB device and program the bootloader.

I believe that the AS3722 power sequencer has powered up everything that should be powered ON in Reset Recovery mode on the Dev Card, here is a comparison between our module and the Dev Card in Reset Recovery Mode:
Tegra K1 Pin TK1 Dev Card Voltage TK1 Module Voltage
CLK_32K_IN 1.8V @ 32.68KHz 1.8V @ 32.68KHz
CLK_32K_OUT 0.0V 0.0V
SYS_RESET_N 1.81V 2.093V
VDD_RTC 1.05V 1.048V
VPP_FUSE 0.0V 0.0V
CORE_PWR_REQ 1.81V 1.79V
+1.05V_LPO_VDD_RTC 1.051V 1.048V
+VDD_CORE 1.10V 1.101
+1.8V_VDDIO 1.81V 1.7995
+1.35V_LP0 1.35V 1.3564
+1.05V_RUN_AVDD 1.051V 1.0465

I’m able to see that the Tegra K1 is outputting a clock to the EMMC memory at pin G31 (SDMMC4_CLK), so it does seem like the K1 is powered ON and attempting to use it’s EMMC interface.

I’m able to detect the Tegra K1 on the JTAG Chain, what functionality does access to the JTAG port on the Tegra K1 give? Am I able to read registers to determine the status of the TK1?

A few questions I have:
• Are there any output signals from the Tegra K1 that clearly indicate that is Powered ON and in Reset Recovery Mode? I do see a reduction of current on the DC supply powering the module when I put the board in Reset Recovery Mode, I took this as a good indication that it is in Reset Recovery Mode.
• After the AS3722 has powered up successfully, is programming the bootloader using FLASH the next step in the bringup process for the Tegra K1?
• How do I communicate with the TK1 over JTAG? I have the BSDL file, is there a suggested application?
Thanks in advance for any advice/suggestions you can provide!
Jeff

If “lsusb” doesn’t show the board, then it’s useless to try running e.g. the flash.sh script.

Some info about the boot flow is here:

ftp://download.nvidia.com/tegra-public-appnotes/tegra-boot-flow.html

Thanks Kulve! Appreciate the assistance.

What is the function of the Board ID ROM? Does the board ID ROM need to be programmed to recognize the TK1 as a USB device? I haven’t been able to find much info on this in the NVidia documentation

I have not built a custom TK1 board so I don’t know much about this chip, but I have seen others with the same difficulty…the chip is involved in flash and has been the cause of others in the past having problems flashing.

How exactly are you entering the forced recovery mode?

I have Push buttons connected to GPIO_PI1 (FORCE_RECOVERY_L) and to XRES_IN of the AS3722, this matches what I see in the TK1 Dev Card schematic. I then hold the Recovery PB, then press and hold the Reset for a minimum of 2 seconds, and then release the Reset PB followed by the Recovery PB.

After doing this I can see on my DC supply that my card is using less current than when the card is not in Recovery Mode, so I took this as a good indication that I was successfully putting it in recovery mode.

Are there any outputs from the TK1 that indicate that its in Recovery Mode?

Thanks! I think it must be involved in flashing the bootloader, because if I remove the Board ID ROM from the TK1 Dev Card I’m no longer able to program the bootloader. I am still able to detect the TK1 Dev Card as a USB Device using lsusb, and do not get the same “USB device not detected error” that I’m seeing on my custom board, so I don’t think that’s the issue that I’m seeing (yet)

When you don’t have a EEPROM with correctly flashed Board Id, BOARDID in jetson-tk1.conf shall be uncommented before executing flash.sh

BOARDID="0x177 0x00 0x03";

Thats right, please try passing a boardid while flashing if you dont have a EEPROM

How long are you keeping the Recover PB pressed after releasing the Reset PB?

I assume you using the correct USB controller for this?

Sorry, no idea about that.

You probably have seen all the HW docs but there are something updated here:
https://developer.nvidia.com/hardware-design-and-development

Thanks theImp! that will definitely save me some time

I’m keeping the Recover PB pressed for probably 1 second after releasing the Reset PB.

I’m using USB0 on the TK1 so I believe I’m using the correct USB controller, but I do have a USB LAN controller connected to USB1, could this be affecting the boot cycle?

FYI, the micro USB OTG connector is in host mode at all times when Jetson isn’t in recovery mode. Your non-Jetson host connected to Jetson via the provided micro-B will never see anything about this Jetson in lsusb until Jetson enters recovery mode (this is when the connector enters device mode instead). Even if flash won’t work for other reasons, seeing the board show up on the host via lsusb is proof of recovery mode.

By the way, the general procedure of going to Recovery Mode is:

  1. Press and HOLD the FORCE RECOVERY button
  2. Now press and release the RESET button.
  3. Now release Force Recovery button

Sorry about the formatting, I can’t figure out how to upload tables of data, but I’ve done a ball-to-ball comparison between the Tegra K1 Dev Card, and my custom TK1 design. Here are all the pins where I saw a difference in voltage:
TK1 Pin Pin Number Dev Card State Custom TK1 State Notes
SDMMC3_CD_N V24 1.786 NC
KB_COL4 AF28 1.789 NC
KB_COL5 AA27 1.814 NC
KB_ROW7 Y30 0.900 NC
JTAG_TDI H5 1.81 0.0
AVDD_LVDS0_PLL AF1 3.31 1.816
UART2_RXD L9 1.81 0.0
GPIO_PB0 U4 1.81 0.0
GPIO_PG5 AA3 1.81 2.5Vpk/pk @ 2.9MHz
GPIO_PI3 V7 1.81 0.0
GPIO_PK1 R3 0.0 NC
GPIO_PK2 Y1 1.81 2.5
GPIO_PK4 T1 1.81 NC
GPIO_PK7 V5 0.0 1.796
GEN2_I2C_SCL Y2 3.31 1.796
GEN2_I2C_SDA AA2 3.31 1.426
PEX_L1_CLKREQ_N AJ30 0.0 3.32
PEX_L0_RST_N AJ29 0.0 3.31

and here are the remainder of the measurements:
TK1 Pin Pin Number Dev Card State Custom TK1 State Notes
VDDIO_BB AC14 1.812 1.816
ULPI_DATA0 AF15 0.0 0.0
ULPI_DATA3 AJ15 0.0 0.0
ULPI_CLK AK17 0.0 NC
ULPI_DIR AL18 0.0 NC
ULPI_NXT AG15 0.0 NC
ULPI_STP AL16 0.0 NC
DAP3_DOUT AE17 0.0 NC
GPIO_PV0 AG17 1.812 1.81
GPIO_PV1 AD15 1.810 1.81
VDDIO_SDMMC1 P9 1.810 1.816
SDMMC1_COMP_PU J7 0.0 0.0
SDMMC1_COMP_PD L6 0.0 0.0
CLK2_OUT K1 0.0 NC
VDDIO_SDMMC3 E1 0.0 0.0
SDMMC3_CLK F5 0.0 NC
SDMMC3_CMD F2 0.0 NC
SDMMC3_CD_N V24 1.786 NC
SDMMC3_COMP_PU E2 0.0 0.0
SDMMC3_COMP_PD E5 0.0 0.0
VDDIO_SDMMC4 F31 1.815 1.816
SDMMC4_CLK G31 No TP 1.816 1.8V pk/pk @ 19.45MHz clock
SDMMC4_CMD E31 1.817 1.816 Appears to be noise/ripple on the 0305 signal
SDMMC3_COMP_PU H30 1.811 1.81
SDMMC3_COMP_PD H29 0.0 0.0
KB_COL0 AD30 1.811 1.798
KB_COL3 AD31 0.900 0.898
KB_COL4 AF28 1.789 NC
KB_COL5 AA27 1.814 NC
KB_ROW0 W31 0.0 NC
KB_ROW2 AF30 No TP NC
KB_ROW4 Y29 0.900 0.898
KB_ROW6 AB31 0.0 NC
KB_ROW7 Y30 0.900 NC
KB_ROW9 AA28 0.0 NC
KB_ROW10 AA31 0.0 NC
KB_ROW16 AA26 0.0 NC
KB_ROW17 AC29 0.0 0.0
VDD_RTC AB12 1.05V 1.048V
PWR_I2C_SCL J4 1.81 1.81
PWR_I2C_SDA J3 1.81 1.81
CORE_PWR_REQ Y28 1.81 1.81
CPU_PWR_REQ V25 0.0 0.0
CLK_32K_IN H3 1.8Vpk/pk @ 32.68KHz 1.8Vpk/pk @ 32.68KHz
CLK_32K_OUT J6 0.0V 0.0V
PWR_INT_N V30 1.81 No TP Going to wire onto a via on bottom of PCB to measure
SYS_RESET_N AA30 1.81V 2.093V
THERMD_P U28 0.0 0.0
THERMD_N U29 0.0 0.0
VPP_FUSE R10 0.0V 0.0V
JTAG_RTCK J2 0.0 No TP
JTAG_TCK H6 0.0 2.5
JTAG_TDI H5 1.81 0.0
JTAG_TDO J1 1.81 2.5
JTAG_TMS J5 1.81 2.5
JTAG_TRST_L H4 1.81 2.5
TEST_MODE_EN H7 0.0 0.0
AVDD_OSC D1 1.81 1.815
XTAL_IN E3 1.0V pk/pk @ 12MHz 1.0V pk/pk @ 12MHz
XTAL_OUT E4 1.8V pk/pk @ 12MHz 1.8V pk/pk @ 12MHz
AVDD_DSI_CSI AK14 0.0 0.0
CSI_A_CLK_N/P AE11/AD11 0.0 NC
CSI_E_CLK_N/P AJ8/AH8 0.0 NC
CSI_DSI_RUP AF11 0.0 NC
CSI_DSI_RDN AG11 0.0 NC
VDDIO_CAM AC11 0.190 NC
GPIO_PCC1 AJ6 0.0 0.060
GPIO_PCC2 AL7 0.0 0.060
GPIO_PBB0 AK5 0.0 0.0
GPIO_PBB3 AK6 0.0 0.0
GPIO_PBB4 AH6 0.0 0.0
GPIO_PBB5 AH5 0.0 0.0
GPIO_PBB6 AL6 0.0 0.0
GPIO_PBB7 AJ5 0.0 0.0
CAM_I2C_SCL AF8 0.180 0.0
CAM_I2C_SDA AG8 0.180 0.0
CAM_MCLK AL5 0.0 NC
VDDIO_HSIC AC15 0.0 NC
HSIC1_DATA AF18 0.0 NC
HSIC_STROBE AE18 0.0 NC
HSIC_REXT AH18 0.0 NC
AVDD_HDMI AA9 3.05 No TP Will add wire to bottom of PCB to measure
AVDD_HDMI_PLL AH1 0.0 0.0
HDMI_TXCP/N AF5/AF6 0.0 0.0
HDMI_CEC AD7 3.25 2.953
HDMI_INT AC3 0.0 0.0
HDMI_RST AF2 0.0 0.0
HDMI_PROBE AE1 NC NC
DDC_SCL (HDMI) AC7 0.0 3.31
DDC_SDA (HDMI) AC8 0.0 3.31
AVDD_LVDS0_IO AJ1 1.044 1.046
AVDD_PLL_UD2DPD AL4 1.051 1.046
AVDD_LVDS0_PLL AF1 3.31 1.816
DP_HPD AC2 0.0 0.0
LVDS0_RSET AK3 0.0 0.0
LVDS0_PROBE AL3 NC NC
DP_AUX_CH0_P/N AC6/AC5 0.0 0.0
AVDD_PLL_UTMIP AB15 1.81 1.81
AVDD_USB AC12 3.32 3.307
USB0D_N/P AH20/AJ20 1.2V @ 240MHz 0.0 Data can clearly be seen on the TK1 Dev card, nothing on the 0305 module
USB1D_N/P AF20/AG20 0.0 0.0
USB2D_N/P AE20/AD20 0.0 0.0
USB_VBUS_EN0 AB1 0.0 0.0
USB_VBUS_EN1 AC1 0.0 0.0
USB0_VBUS AL20 3.31 3.31
USB0_ID AK20 0.0 NC
USB_REXT AL19 0.951 No TP
VDDIO_UART U10 1.81 1.812
UART2_RXD L9 1.81 0.0
UART2_TXD M8 1.83 1.812
UART2_CTS_N M1 1.81 NC
UART2_RTS_N P4 1.81 NC
CLK3_OUT P7 0.0 NC
GPIO_PU0 R7 0.0 NC
GPIO_PU1 P2 0.0 NC
GPIO_PU2 M10 0.0 NC
GPIO_PU3 P8 0.0 NC
GPIO_PU4 M9 0.0 NC
GPIO_PU5 M4 0.0 NC
GPIO_PU6 M5 0.0 NC
GEN1_I2C_SCL P6 1.81 1.81
GEN1_I2C_SDA M6 1.81 1.81
DAP1_DOUT L28 0.0 NC
DAP_MCLK1 L29 0.0 NC
DAP_MCLK1_REQ M31 0.0 NC
DAP2_DIN L30 NC NC
DAP2_DOUT J29 NC NC
DAP2_FS R30 NC NC
DAP2_SCLK M29 0.0 NC
SPDIF_IN AA8 0.0 No TP
VDDIO_HV Y10 3.314 3.31
VDDIO_GMI U9 1.812 1.81
GPIO_PB0 U4 1.81 0.0
GPIO_PB1 V9 0.0 No TP
GPIO_PG0 V2 1.81 1.81
GPIO_PG1 V6 1.81 1.81
GPIO_PG2 Y7 0.0 0.0
GPIO_PG3 AA5 1.81 1.81
GPIO_PG4 Y3 1.81 1.81
GPIO_PG5 AA3 1.81 2.5Vpk/pk @ 2.9MHz
GPIO_PG6 Y8 0.0 1.81
GPIO_PG7 V3 0.0 1.81
GPIO_PH1 U3 0.0 No TP
GPIO_PH2 AA4 0.0 No TP
GPIO_PH4 R5 NC No TP
GPIO_PH7 U2 1.77 No TP
GPIO_PI0 Y5 1.81 No TP
GPIO_PI1 AA6 1.81 1.81
GPIO_PI3 V7 1.81 0.0
GPIO_PI6 R1 1.81 No TP
GPIO_PJ0 U6 0.441 NC
GPIO_PJ7 V4 0.0 0.0
GPIO_PK1 R3 0.0 NC
GPIO_PK2 Y1 1.81 2.5
GPIO_PK4 T1 1.81 NC
GPIO_PK7 V5 0.0 1.796
GEN2_I2C_SCL Y2 3.31 1.796
GEN2_I2C_SDA AA2 3.31 1.426
SDMMC2_COMP_PU U5 0.0 No TP
SDMMC2_COMP_PD R6 0.0 No TP
GPIO_X1_AUD P29 0.0 0.0
GPIO_X4_AUD R28 0.0 0.0
GPIO_X7_AUD P28 0.0 NC
DVFS_PWN P30 0.0 No TP
DVFS_CLK R29 1.81 No TP
HVDD_SATA AF31 3.31 3.31
VDDIO_SATA_PLL AH31 0.0 0.0
SATA_TESTCLKP/N AG27/AF27 0.0 No TP
SATA_TERMP AL25 0.0 No TP
AVDD_PLL_C4 P10 1.04 1.044
AVDDIO_PEX AB17 0.0 0.0
HVDD_PEX_PLL_E AL28 3.31 3.31
AVDD_PEX_PLL AC21 0.0 0.0
AVDD_PLL_EREFE AG31 1.051 1.05
AVDD_PLL_X L31 1.047 1.05
USB3_TX0P/N AJ21/AH21 0.0 NC
USB3_RX0P/N AL21/AK21 0.0 NC
PEX_TX2_C_P/N AJ23/AH23 0.0 0.0
PEX_RX2_P/N AE21/AD21 0.0 No TP
PEX_TX4_P/N AH26/AJ26 0.0 0.0
PEX_RX4_P/N AL26/AK26 No TP 0.0
PEX_CLK1_P/N AF26/AG26 0.0 0.0
PEX_CLK2_P/N AC26/AC27 0.0 0.0
PEX_TESTCLKP/N AF24/AG24 NC NC
PEX_TERMP AL22 0.0 No TP
VDDIO_PEX_VTL AE31 3.31 3.31
PEX_L0_RST_N AJ29 0.0 3.31
PEX_L1_RST_N AJ31 0.0 0.0
PEX_L0_CLKREQ_N AK29 0.0 0.0
PEX_L1_CLKREQ_N AJ30 0.0 3.32
PEX_WAKE_N AG28 3.34 3.32
GPIO_PFF2 AG30 NC 2.95
USB_VBUS_EN2 AG29 NC 0.0
DDR_CLKN/P G14/H14 0.0 0.0
DDR_CLKB_N/P H18/G18 0.0 0.0
DDR_CAS_N C15 No TP No TP
DDR_RAS_N D15 No TP No TP
DDR_WE_N E15 No TP NC
DDR_RESET_N F15 No TP NC
DDR_COMP_PU C17 1.348 No TP
DDR_COMP_PD D17 0.0 No TP
AVDD_PLL_M K16 1.045 1.044
VDDIO_DDR_1 J9 1.353 1.185
VDDIO_DDR_MCLK J15 1.34 1.185
VDD_CORE AA13 1.10V 1.101V
VDD_CPU R23 0.0 0.0
VDD_GPU AA23 0.0 0.0

Still trying to work through this issue, does anyone know if pin K31 - VDDIO_AUDIO is required for startup?

Currently I have this pin not connected on my design, so I don’t have access to this to connect +1.8V, but it is listed in the startup process of the Design Guide. Unfortunately the Jetson TK1 Dev Card has this pin connected directly to +1.8V, so there is no way for me to remove the voltage from the Dev Card to attempt to cause it to fail.

Our design also leaves VDDIO_CAM disconnected, so this is another potential issue.

Was wondering if anyone has any experience/success with a design where VDDIO_AUDIO or VDDIO_CAM were left NC
Thanks

Was able to determine the problem. My schematic mistakenly had two nets for +3.3V_LPO, one named +3.3V_LPO, the other named +3.3V_LP0, which had no source and was connected to AVDD_USB. Thanks to everyone who chimed in to help!

Hi, Where is this configuration? I can’t find