No changes in generated pinmux when changing PEX_C5_CLKREQ_N

When changing the configuration of the PEX_C5_CLKREQ_N (c8) pin in the pinmux configuration spreadsheet, the changes are not visible in the output .cfg file (the PEX_L5 pin isn’t inside the generated .cfg file at all, but it is in the dtsi file generated by the template. Is this correct behavior?

When manually adding these rows to the pinmux file, a boot error occurs in MB1
pinmux.0x02444000 = 0x00000560; # pex_l5_clkreq_n_pgg0: pe5, tristate-disable, input-enable, io_high_voltage-enable, lpdr-enable
pinmux.0x02444008 = 0x00000520; # pex_l5_rst_n_pgg1: pe5, tristate-disable, input-disable, io_high_voltage-enable, lpdr-enable

This causes the following error:
[0006.332] !!! Exception !!! [lr:0x40032a8e, dfar:0x2444000, dfsr:0x1808]
[0006.339] C> MB1( BIT boot status dump :

So can this pin (PEX_C5_CLKREQ_N ) be configured?


Generally this pin does not need to be configured by pinmux. What is the purpose here?

We wanted to configure the pin as we get a crash similar to this thread: Micron SSD not recognized by Jetson AGX Xavier.
In the linked thread, the issue was the PCIe clock and it’s configuration in the pinmux file (boot crash with specific SSDs, fixed by setting the PCIe clock to a certain configuration in the pinmux). Therefore, I wanted to configure this PEX L5 clock pin similarly but noticed that the changes in the pinmux are not generated into the pinmux file at all.

Currently, we see the same symptoms as the linked thread, but in a different situation. As we see the crash when an FPGA connected to the PCIe bus of the Jetson restarts when the Jetson is booting while in the UEFI boot step.

So this pin (PEX L5) cannot be configured, right?

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