I’m trying to connect the Jetson TX1 over PCIe to my FPGA-design. I didn’t wire the ClkReq-signal into my design, so I have to permanently enable the RefClk-signal from the Tegra. For this I added the “nvidia,disable-clock-request” attribute to “pci@1,0” and “pci@2,0” in the device-tree file. But there is still no permanent RefClk-signal generated.
For debugging I put the Jetson back onto the developer-kit board and tried to probe the pins of the PCIe-connector with an oscilloscope (Rigol DS2202). With this I can see that while system boot the 100MHz ref-signal is there for about a second, but then it vanishes.
Do you have an idea what might be the problem?
This is just a wild guess, but you may want to make sure no power saving type mode is kicking in. See the performance info here for setting max:
I think my problem was that the “nvidia,disable-clock-request”-property is not intended to do what I initially assumed. It does not let the refclk run independently from the current state of the pcie-controller, but it just allows devices to be used which can’t control the clkreq-signal. And if there is no link established the refclk still is disabled.
The refclk is turned on for about 20ms while bus-enumeration. If no link could be established, it is turned off. It is also turned on for a second after powering the Tegra, but this seems to be irrelevant behavior (not controlled by a driver).