Nvidia agx-orin spi1 with CY15B104QN

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

Hello all,

We are trying to get CY15B104QN spi-fram with nvmem subsystem. When we use atmel at25 eeprom driver, we always read FF from the chip. When we try to debug using spi-tools without the driver, if we read with default bits-per-word parameter which is 8 we always read FF. We observed that the spi controller does not drive clock more than 8 bits. If I set bits-per-word to 16 on spi-tools (spi-pipe command) I can read the device id. What could be the problem here? The IC is connected to the SPI1.

		spi@3210000{ /* SPI1 in 40 pin conn */
			status = "okay";
			fram@0 {
        		#address-cells = <1>;
        		#size-cells = <1>;
        		compatible = "atmel,at25", "cypress,fm25";
        		reg = <0x0>;
        		spi-max-frequency = <6250000>;
				pagesize = <1>;
				size = <0x00080000>;
				address-width = <24>;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,tx-clk-tap-delay = <32>;
				};
        		partition@0 {
            		label = "nvstorage";
            		reg = <0x00000000 0x00080000>;  /* 512 KB */
					#nvmem-cell-cells = <0>;
        		};
    		};
		};

or

		spi@3210000{ /* SPI1 in 40 pin conn */
			status = "okay";
			spi@0 { /* chip select 0 */
				compatible = "tegra-spidev";
				reg = <0x0>;
				spi-max-frequency = <6250000>;
			};
		};
5

Hi yavuz.mutlu,

Are you using the devkit or custom board for AGX Orin?
What’s the Jetpack version in use?

Do you have any concern to use bits-per-word as 16?

In 16-bit mode, the command and address bytes are grouped into the same SPI transfer, ensuring they are sent in one continuous transaction. This prevents chip-select(CS) from toggling or introducing gaps between bytes, which could otherwise cause the device to misinterpret the sequence and lead to data loss.

6

Hello,

It is a custom carrier board. Jetpack version is 36.4.3. Where should I add bits-per-word param in the device tree? I tried like this.

		spi@3210000{ /* SPI1 in 40 pin conn */
			status = "okay";
			fram@0 {
        		#address-cells = <1>;
        		#size-cells = <1>;
        		compatible = "atmel,at25", "cypress,fm25";
        		reg = <0x0>;
        		spi-max-frequency = <6250000>;
                bits-per-word = <16>;
				pagesize = <1>;
				size = <0x00080000>;
				address-width = <24>;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,tx-clk-tap-delay = <32>;
				};
        		partition@0 {
            		label = "nvstorage";
            		reg = <0x00000000 0x00080000>;  /* 512 KB */
					#nvmem-cell-cells = <0>;
        		};
    		};
		};

If so it did not work either in my case.

Thanks.

11

Could you apply the patch from the following thread to check if it could help for your case?
Jetson orin nano SPI Speed not changing - #9 by KevinFFF

It may be handled by your custom driver as you are using atmel,at25 and cypress,fm25 as following.

12

Hi,

I already applied this patch while I was integrating another spi slave to spi2 controller.

13

Please note that SPI2(c260000.spi) is from SPE.