NVIDIA Jetson AGX Xavier custom carrier board 9pin CLK125 not connect

background:NVIDIA Jetson AGX Xavier custom carrier board
In the P2822_B03 schematic diagram, RGMII is converted into gigabit network through the network chip 88E1512. The 9pin CLK125 of 88E1512 is not connected to the AGX core board. The 125MHz clock generated by this pin is used for data transmission. Why is it not connected to the AgX? Will it affect data transmission? In addition, must 12Pin int be connected to AGX? Will it be affected if you don’t answer?

If you want to use same PHY 88E1512PB2, please just follow the reference design to keep pin 9 float and connect pin12 to AGX. That has been validated on devkit.

I don’t use PHY 8831512PB2, i want use PHY KSZ9031, Is 125MHz clock also keep float, Does AgX need this clock?

Please refer to the datasheet of custom PHY and check with its vendor for design.