Can you please tell me if there is any existing documentation on the Denver 2 CPU core execution latencies? ARM provides a software optimization guide for the A57 core that provides details on the execution latency of for example the “FADD” instruction of 5 cycles. Does there exist any documentation that describes the same type of information on the execution latencies for all instructions for the Denver 2 core?
We’re going to check if any doc available to be provided, please wait for our update.
I just want to check on the progress on maybe providing me with such documentation if possible?
We are checking if can public relative document, will update once get any result.
Attached the document here for reference.
Parker-SW-Optimization-Guide_DA07334001_v1.0.pdf (367.8 KB)
This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.