NVIDIA Orin AGX: GICv2m memory range question

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
,
1

Dear all,

interrupt-controller@f400000 {
#redistributor-regions = <0x01>;
compatible = “arm,gic-v3”;
ranges;
#interrupt-cells = <0x03>;
status = “okay”;
reg = <0x00 0xf400000 0x00 0x10000 0x00 0xf440000 0x00 0x200000>;
phandle = <0x01>;
interrupt-controller;

v2m@f410000 {
	arm,msi-num-spis = <0x46>;
	reg-names = "gic_base\0msi_base";
	arm,msi-base-spi = <0x260>;
	msi-controller;
	compatible = "arm,gic-v2m-frame";
	reg = <0x00 0xf410000 0x00 0x10000 0x00 **0x54000000** 0x00 **0x4000000**>;
	phandle = <0x11>;
	#msi-cells = <0x01>;
};

};

I’m wondering what is this memory range used for [0x5400_0000, 0x400_0000]? Other question is which device driver probes this node on NVIDIA ORIN AGX?
Either:

  • pcie-tegra194.c
  • irq-gicv2m.c

Thanks in advance,
Jorge

3

From the defconfig the pcie-tegra194.c enable for the kernel.

4

Thanks for your prompt response. Please, see below:

static int tegra_pcie_msi_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);

writel(lower_32_bits(pcie->gic_base.start + V2M_MSI_SETSPI_NS),
       pcie->appl_base + APPL_SEC_EXTERNAL_MSI_ADDR_L);
writel(upper_32_bits(pcie->gic_base.start + V2M_MSI_SETSPI_NS),
       pcie->appl_base + APPL_SEC_EXTERNAL_MSI_ADDR_H);

writel(lower_32_bits(pcie->msi_base.start),
       pcie->appl_base + APPL_SEC_INTERNAL_MSI_ADDR_L);
writel(upper_32_bits(pcie->msi_base.start),
       pcie->appl_base + APPL_SEC_INTERNAL_MSI_ADDR_H);

return 0;

}

pcie->gic_base.start (0xf41_0000) and pcie->msi_base.start (0x5400_0000) are being set in the APPL_SEC_ registers. INTERNAL and EXTERNAL.

It seems GICv2m is the external MSI controller while some secret NVIDIA IP is used an internal MSI controller. In the TRM, it says GIC_MSI has the base address of 5400_0000, but I do not find any other information.

Are both INTERNAL and EXTERNAL MSI controllers being used?

Could you please provide some documentation about the INTERNAL MSI (the so-called GIC_MSI that is not GICv2m)?

Best,
Jorge