ODMDATA bit definitions for PCIe C0 port end point mode?

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hello,

Can you show the ODMDdata bit definitions or documets which define them?

In Adaption Guide, ODMDDATA[31:27,24:22] are defined, but the other bits are not
defined.

Especially, I am looking for the way to configure the pcie C0 to endpoint mode.
So, it would be helpful to share the concerns of setting pcie C0 end point mode
on the Xavier DevKit.

As far as I know, pcie clock for the C0 is output to the M.2 card edge on Xavier
devkit even when it is at endpoint mode. My M.2 device can handle that, but I am
not sure PCIe C0 port in Xavier can work with that configuration.

  • References
  1. Tegra_Linux_Driver_Package_AGX_Xavier_Adaptation_Guide.pdf
  2. Jetson_AGX_Xavier_OEM_Product_Design_Guide.pdf
  3. Jetson_AGX_Xavier_PCIe_Endpoint_Design_Guidelines.pdf
  4. Xavier_TRM_DP09253002.pdf

Thank you in avdance,
shino

2

Hi,

bit 26 is for C0 1/0: enable/disable ep mode.
bit 25 for C4
bit 12 for C5.

Please let us know if it does not work. Thanks.

3

I appreciate your really quick response.

This helps us so much!

– shino