Looking at the AMAP section in the Orin TRM, I notice this “off-chip aperture” region.
Could you please explain how these BOM/TOM registers mentioned here can be configured? Is there any other configuration that needs to be done on the Orin SoC to allow usage of this region? Couldn’t find other mentions in forums or docs.
Use-case is to use a carveout in this address space for ‘prefetchable’ BAR region for a device connected to the Orin’s PCIe root-port controller C5.
Hi dj45,
Are you using the devkit or custom board for AGX Orin?
What’s the Jetpack version in use?
Please check if the following guide could help for your case.
PCIe Endpoint Mode — NVIDIA Jetson Linux Developer Guide
Hi, I’m using a custom carrier on Jetpack6, Rel 36.4.3.
That link is for when the controller is configured as end-point mode, right? My use-case is for when C5 is configured as a root-port.
Is there anything in the iATU section of the Synopsys designware core driver that needs to be configured to allow use of the off-chip aperture section in the Orin AMAP?
Configuring this is now allowed as our previous check with internal team.
