Looking at the AMAP section in the Orin TRM, I notice this “off-chip aperture” region.
Could you please explain how these BOM/TOM registers mentioned here can be configured? Is there any other configuration that needs to be done on the Orin SoC to allow usage of this region? Couldn’t find other mentions in forums or docs.
Use-case is to use a carveout in this address space for ‘prefetchable’ BAR region for a device connected to the Orin’s PCIe root-port controller C5.
Hi dj45,
Are you using the devkit or custom board for AGX Orin?
What’s the Jetpack version in use?
Please check if the following guide could help for your case.
PCIe Endpoint Mode — NVIDIA Jetson Linux Developer Guide
Hi, I’m using a custom carrier on Jetpack6, Rel 36.4.3.
That link is for when the controller is configured as end-point mode, right? My use-case is for when C5 is configured as a root-port.
Is there anything in the iATU section of the Synopsys designware core driver that needs to be configured to allow use of the off-chip aperture section in the Orin AMAP?
Configuring this is now allowed as our previous check with internal team.
I created this separate issue here with a more detailed crash log when trying to access this region, could you please take a look to see if something stands out to you?
The first error I see is:
ERROR: RAS Uncorrectable Error in SCC, base=0xe016000:
ERROR: Status = 0xe400090d
ERROR: SERR = Illegal address (software fault): 0xd
ERROR: IERR = Address Range Error: 0x9
ERROR: MISC0 = 0x6000000
ERROR: MISC1 = 0xc1a75
ERROR: MISC2 = 0x0
ERROR: MISC3 = 0x0
ERROR: ADDR = 0x8000005000ff6f40
ERROR: **************************************
Could you please suggest a simpler test I could do with tools like devmem or the likes? I’d like to at least verify that the address I’m trying to poke is recognized as valid by the SoC. I guess if that poke times out or results in a read failure, and not an early illegal-access error, then the mapping is at least valid?