omg, I'm confused with memory banks

[GoGdizzY]

forgive my poor English,

the banks are organized such that successive 32-bit words are assigned to successive banks and each bank has a bandwidth of 32 bits per two clock cycles.

if I have 256 bytes, is that means

addr: 0 4 8 12 16 20 24…

bank: 0 1 2 3 4 5 6…

OR

addr: 0-15 16-31 32-47 … 240-255

bank: 0 1 2 … 15

[Nico]

The first case.

N.