On jetson AGX Orin SPI enable as a slave

Hi

Actually, I want enable SPI communication on jetson agx orin as a slave, is this possible. If possible, how can I set as a slave. Could you please refer an link or steps to set this one as a slave.

Actually my requirement is Renesas RH850F1KM is a master (both transmission and reception) .

Hello,

I am moving your post to the Jetson forums for better visibility.

Cheers,
Tom

Hi eduri.lavanya,

Are you using the devkit or custom board for AGX Orin?
What’s your Jetpack version in use?

You could refer to the following thread to configure the SPI as slave.
SPI0 interface configured as a slave in Jetson Xavier NX - #10 by borjabasket14

Hi KevinFFF

Using Jetson AGX Orin dev kit
And jetpack version 5.1.2
Jetson Linux_R35.4.1

Thank you

Have you referred to that thread to configure the compatible in SPI node to enable SPI slave?

Please share the full dmesg for further check.

You can also get a scope to measure the signal from both sides.

Hi

Please check the text file (full dmesg).

Thank you
dmesg_spi.txt (75.1 KB)

[    4.493478] spi-tegra124-slave c260000.spi: Reset control is not found

It seems your the reset for spi-slave is failed.
Please share the full device tree for further check.

Hi
tegra234-p3701-0000-p3737-0000.dts

/*

  • Top level DTS file for CVM:P3701-0000 and CVB:P3737-0000.
  • Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
  • This program is free software; you can redistribute it and/or modify
  • it under the terms of the GNU General Public License as published by
  • the Free Software Foundation; version 2 of the License.
  • This program is distributed in the hope that it will be useful, but WITHOUT
  • ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  • FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  • more details.tegra234-p3737-0000-a04.dtsi
    */

/dts-v1/;
include “tegra234-p3701-0000-prod.dtsi”
include “cvm/tegra234-p3701-0000.dtsi”
include “cvb/tegra234-p3737-0000-a04.dtsi”
include “tegra234-power-tree-p3701-0000-p3737-0000.dtsi”
include “tegra234-dcb-p3701-0000-a02-p3737-0000-a01.dtsi”
include <tegra234-soc/mods-simple-bus.dtsi>
include “cvb/tegra234-p3737-camera-modules.dtsi”
include <t234-common-cvb/tegra234-pwm.dtsi>
include <t234-common-cvm/tegra234-cpuidle.dtsi>
include <t234-common-cvm/tegra234-thermal.dtsi>
include <t234-common-cvm/tegra234-thermal-cooling.dtsi>
include <t234-common-cvm/tegra234-thermal-userspace-alert.dtsi>
include <tegra234-soc/tegra234-soc-hwpm.dtsi>

/ {
nvidia,dtsfilename = FILE;
nvidia,dtbbuildtime = DATE, TIME;

compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234", "nvidia,tegra23x";
model = "Jetson AGX Orin Developer Kit";

nvsciipc-kernel {
	compatible = "nvidia,nvsciipc";
	status = "okay";
};

firmware {
	android {
		compatible = "android,firmware";
		first_stage_delay = "1";
		system_root_blkdev = "/dev/mmcblk0p1";
		fstab {
			compatible = "android,fstab";
			vendor {
				compatible = "android,vendor";
				dev = "/dev/block/platform/3460000.sdhci/by-name/vendor";
				type = "ext4";
				mnt_flags = "ro,noatime";
				fsmgr_flags = "wait";
			};
		};
	};
};

display@13800000 {
	status = "okay";
};

dce@d800000 {
	status = "okay";
};

bpmp {
	i2c {
		tegra_tmp451: temp-sensor@4c {
			vdd-supply = <&p3737_vdd_1v8_sys>;

			ext {
				shutdown-limit = <107>;
			};
		};

		vrs11_1@20 {
			compatible = "nvidia,vrs11";
			reg = <0x20>;
			rail-name-loopA = "GPU";
			rail-name-loopB = "CPU";
			status = "okay";
		};

		vrs11_2@22 {
			compatible = "nvidia,vrs11";
			reg = <0x22>;
			rail-name-loopA = "SOC";
			rail-name-loopB = "CV";
			status = "okay";
		};
	};
};

reserved-memory {
	linux,cma {
		status = "okay";
	};
};

tegra_soc_hwpm {
            status = "okay";
    };

tegra-hsp@3d00000 {
	status = "okay";
};

aon@c000000 {
	status = "okay";
};

cpu_alert: cpu-throttle-alert {
	status = "okay";
};

gpu_alert: gpu-throttle-alert {
	status = "okay";
};

cv0_alert: cv0-throttle-alert {
	status = "okay";
};

cv1_alert: cv1-throttle-alert {
	status = "okay";
};

cv2_alert: cv2-throttle-alert {
	status = "okay";
};

soc0_alert: soc0-throttle-alert {
	status = "okay";
};

soc1_alert: soc1-throttle-alert {
	status = "okay";
};

soc2_alert: soc2-throttle-alert {
	status = "okay";
};

hot_surface_alert: hot-surface-alert {
	status = "okay";
};

stm@24080000 {
	status = "disabled";
};

cpu0_etm@27040000 {
	status = "disabled";
};

cpu1_etm@27140000 {
	status = "disabled";
};

cpu2_etm@27240000 {
	status = "disabled";
};

cpu3_etm@27340000 {
	status = "disabled";
};

cpu4_etm@27440000 {
	status = "disabled";
};

cpu5_etm@27540000 {
	status = "disabled";
};

cpu6_etm@27640000 {
	status = "disabled";
};

cpu7_etm@27740000 {
	status = "disabled";
};

cpu8_etm@27840000 {
	status = "disabled";
};

cpu9_etm@27940000 {
	status = "disabled";
};

cpu10_etm@27A40000 {
	status = "disabled";
};

cpu11_etm@27B40000 {
	status = "disabled";
};

funnel_ccplex0@26030000 {
	status = "disabled";
};

funnel_ccplex1@26040000 {
	status = "disabled";
};

funnel_ccplex2@26050000 {
	status = "disabled";
};

funnel_top_ccplex@26020000 {
	status = "disabled";
};

funnel_major@24040000 {
	status = "disabled";
};

replicator@24060000 {
	status = "disabled";
};

etf@24050000 {
	status = "disabled";
};

etr@24070000 {
	status = "disabled";
};

serial@31d0000 {
	status = "okay";
};

        mttcan@c310000 {
            status = "okay";
    };

    mttcan@c320000 {
            status = "okay";
    };
 spi1: spi@c260000 {
            compatible = "nvidia,tegra186-spi-slave";
            status = "okay";
    };

};

===================================================================================
tegra234-soc-spi.dtsi

/*

  • Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
  • This program is free software; you can redistribute it and/or modify it
  • under the terms and conditions of the GNU General Public License,
  • version 2, as published by the Free Software Foundation.
  • This program is distributed in the hope it will be useful, but WITHOUT
  • ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  • FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  • more details.
  • You should have received a copy of the GNU General Public License
  • along with this program. If not, see http://www.gnu.org/licenses/.
    */

/ {
aliases {
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi6 = &qspi0;
spi7 = &qspi1;
};

spi0: spi@3210000 {
	compatible = "nvidia,tegra186-spi";
	reg = <0x0 0x03210000 0x0 0x10000>;
	interrupts = <0 36 0x04>;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu_niso0 TEGRA_SID_NISO0_GPCDMA_0>;
	dma-coherent;
	dmas = <&gpcdma 15>, <&gpcdma 15>;
	dma-names = "rx", "tx";
	spi-max-frequency = <65000000>;
	nvidia,clk-parents = "pll_p", "clk_m";
	clocks = <&bpmp_clks TEGRA234_CLK_SPI1>,
		<&bpmp_clks TEGRA234_CLK_PLLP_OUT0>,
		<&bpmp_clks TEGRA234_CLK_CLK_M>;
	clock-names = "spi", "pll_p", "clk_m";
	resets = <&bpmp_resets TEGRA234_RESET_SPI1>;
	reset-names = "spi";
	status = "disabled";

};

spi1: spi@c260000 {
	compatible = "nvidia,tegra186-spi";
	reg = <0x0 0x0c260000 0x0 0x10000>;
	interrupts = <0 37 0x04>;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu_niso0 TEGRA_SID_NISO0_GPCDMA_0>;
	dma-coherent;
	dmas = <&gpcdma 16>, <&gpcdma 16>;
	dma-names = "rx", "tx";
	spi-max-frequency = <65000000>;
	nvidia,clk-parents = "pll_p", "osc";
	clocks = <&bpmp_clks TEGRA234_CLK_SPI2>,
		<&bpmp_clks TEGRA234_CLK_PLLAON>,
		<&bpmp_clks TEGRA234_CLK_OSC>;
	clock-names = "spi", "pll_p", "osc";
	resets = <&bpmp_resets TEGRA234_RESET_SPI2>;
	reset-names = "spi";
	status = "disabled";
};

spi2: spi@3230000 {
	compatible = "nvidia,tegra186-spi";
	reg = <0x0 0x03230000 0x0 0x10000>;
	interrupts = <0 38 0x04>;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu_niso0 TEGRA_SID_NISO0_GPCDMA_0>;
	dma-coherent;
	dmas = <&gpcdma 17>, <&gpcdma 17>;
	dma-names = "rx", "tx";
	spi-max-frequency = <65000000>;
	nvidia,clk-parents = "pll_p", "clk_m";
	clocks = <&bpmp_clks TEGRA234_CLK_SPI3>,
		<&bpmp_clks TEGRA234_CLK_PLLP_OUT0>,
		<&bpmp_clks TEGRA234_CLK_CLK_M>;
	clock-names = "spi", "pll_p", "clk_m";
	resets = <&bpmp_resets TEGRA234_RESET_SPI3>;
	reset-names = "spi";
	status = "disabled";
};

qspi0: spi@3270000 {
	compatible = "nvidia,tegra23x-qspi";
	reg = <0x0 0x3270000 0x0 0x10000>;
	interrupts = < 0 35 0x04 >;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu_niso1 TEGRA_SID_NISO1_QSPI0>;
	dma-coherent;
	dma-names = "rx", "tx";
	spi-max-frequency = <204000000>;
	nvidia,clk-parents = "pllc", "pll_p";
	clocks = <&bpmp_clks TEGRA234_CLK_QSPI0_2X_PM>,
		 <&bpmp_clks TEGRA234_CLK_QSPI0_PM>,
		 <&bpmp_clks TEGRA234_CLK_PLLC>,
		 <&bpmp_clks TEGRA234_CLK_PLLP_OUT0>;
	clock-names = "qspi", "qspi_out", "pllc", "pll_p";
	resets = <&bpmp_resets TEGRA234_RESET_QSPI0>;
	reset-names = "qspi";
	status = "disabled";
};

qspi1: spi@3300000 {
	compatible = "nvidia,tegra23x-qspi";
	reg = <0x0 0x3300000 0x0 0x10000>;
	interrupts = < 0 39 0x04 >;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu_niso1 TEGRA_SID_NISO1_QSPI1>;
	dma-coherent;
	dma-names = "rx", "tx";
	spi-max-frequency = <204000000>;
	nvidia,clk-parents = "pllc", "pll_p";
	clocks = <&bpmp_clks TEGRA234_CLK_QSPI1_2X_PM>,
		 <&bpmp_clks TEGRA234_CLK_QSPI1_PM>,
		 <&bpmp_clks TEGRA234_CLK_PLLC>,
		 <&bpmp_clks TEGRA234_CLK_PLLP_OUT0>;
	clock-names = "qspi", "qspi_out", "pllc", "pll_p";
	resets = <&bpmp_resets TEGRA234_RESET_QSPI1>;
	reset-names = "qspi";
	status = "disabled";
};

};

Which SPI interface would you like to use?

Have you configured the pinmux before using SPI?
If so, please share how you configure them in pinmux spreadsheet.

I would also like to check how you connect the Renesas RH850F1KM on the AGX Orin devkit. (i.e. which pins are you using?)

Hi

Which SPI interface would you like to use?
SPI1 Interface

Have you configured the pinmux before using SPI?
yes (19 21 23 24 )

pinmux spreadsheet.
image
Orin -RH850f1km
6 - 1
24 -2
21 - 3
19 - 4
23 - 5

Please share the screenshot for the part how you configure the SPI pins.

For SPI1 from 40-pins expansion header (J30), you should enable/configure the node spi@3210000 in tegra234-p3701-0000-p3737-0000.dts device tree.

It seems you were enabling the wrong one as following.

 spi1: spi@c260000 {
            compatible = "nvidia,tegra186-spi-slave";
            status = "okay";
    };

Hi

Yes, we made changes in DTS

spi1: spi@3210000 {
compatible = “nvidia,tegra186-spi-slave”;
status = “okay”;
};

Code for the SPI slave,

slave.zip (1.8 KB)

Master is sending the data properly but Jetson AGX Orin SPI slave not receiving the correct data, It Is receiving Garbage values like below fig

image

What’s the issue here ?
Why it’s receiving Garbage values ?

Thank you in advance

Can you get a scope to check if the waveform is expected?
You should confirm the level of SPI master and SPI slave are the same. (1.8V or 3.3V)

as a clarification
for spidev 0.0 as a slave what needs to be the changes in the dts/dtsi files that need to do like
which spi should i configure is it 260000 or 3210000 and is it spi1 or spi0 that i need configure
and any other changes
I’m still under a confusion so

Thank You
Lavanya

3210000, which is for SPI from 40-pins expansion header.

c260000 is for SPI from SPE.