One OS controlling two Xavier chips

Is there a solution for one OS to control two Xavier chips when designing a product with dual Xavier?

Please refer to Jetson AGX Xavier PCIe Endpoint Design Guidelines App Note

Thanks for the App Note.
but further more than PCIe connection, we want to use one Operation System to control dual Xavier SOC source, just like computer cluster, is there a App Note about that?

You can refer to below topics:
https://devtalk.nvidia.com/default/topic/1058328/jetson-agx-xavier/jetson-xavier-connected-to-multiple-jetson-xaviers-using-pcie/

Thanks for OpenMPI

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