We designed custom carrier board for TX1/TX2 with TI FPDLink deserializer DS90UB940 which is connected to the MIPI-CSI2 bus of the Jetson SOM.
Video capturing works well with installed TX1. But with installed TX2 - only each of the second frame can be captured and it doesn’t depend on video timings.
Workaround for that is to increase the time between FrameEnd and FrameStart packets (CSI low level protocol) on the CSI transmitter side of DS90UB940.
It seems like a known issue and several related topics can be found on the forum. But solution is always workaround on the CSI transmitter side.
I suspect that it is related to some limitation of new TX2 VI architecture where RTCPU was introduced which detects, timestamps and populate frame start event to the VI driver. For some reason it misses FS for each of the second frame when time btw FE and FS less some threshold. I’m not sure if it is SW (rtcpu firmware) or HW limitation and I didn’t find anything in the spec of TX2.
Because time between FE and FS packets cannot always be changed on some of the CSI transmitters - can you share the limitations?
Also if it is SW limitation of RTCPU - is it possible to get source code so we can modify it for our needs? Or can you suggest please some other approaches - for example - to tweak RTCPU clock etc.
Is there any tegra camera driver for TX2 which does not use RTCPU like it was implemented for TX1?