Does anyone have some info on how address space of 24GB of GDDR6 on RTX3090 is distributed on those Micron chips (12 at side of GPU and 12 at back side). Each chip is 8Gbit density of 32 bit data width, which is equal to 256M DWORDS = 1 Gbyte per chip and total of 24GB with 24 chips. But I need info on how those are mapped into address space. For example, does lower address space from 0 to12GB is mapped to chips at GPU side and range from 12GB to 24GB at opposite side, or chips are somehow interleaved?