Orin AGX 2 devices on one PCIe block

[bennaimomer]

Hi,
I would like to know if it possible to connect 2 devices on the same PCIe UPHY1 block
In Jetson AGX Orin functions config #1 we would like to connect:

• m.2 key-m 4 PCIe lanes to UPHY1 L0-L3 to use NMVe devices
• m.2 key-b 2 PCIe lanes to UPHY1 L6-L7

Is it possible?

Thanks in advance,
Omer.

[Manikanta]

Hi,

It is possible. UPHY1 config#2( nvhs-uphy-config-2) configures C5 x4(L0-L3) and C6 x4(L4-L7). Since Tegra PCIe can support lane reversal link can come up in x2 with L7 & L6. Use UPH1 L7 as logical L0 and L6 as logical L1.

Thanks,
Manikanta

[bennaimomer]

Thank you Mainikanta,
You wrote that this is possible in config#2 but we want to use config#1, I assume it will be okay, am I right?
Do I have to link L7 as L0 and L6 as L1 or I can connect it as non-reversal (L7 to L1 and L6 to L0)?

Thanks,
Omer

[Manikanta]

Hi,

No, you need two controller C5 & C6 for two slots, you need to use config#2.
link L7 as L0 and L6 as L1.

Thanks,
Manikanta

[sundaoyu]

Hi Manikanta,
how can i change UPHY mode to configuration #2. Is there any example or documents?
Thanks.

[sundaoyu]

Hi Manikanta,
how can i change UPHY mode to configuration #2. Is there any example or documents?
Thanks.

[Manikanta]

Hi,

I discussed internally. UPHY1(configuration #2) can support only C5 x8 as RP or EP.
Both C5 and C6 are not supported in UPHY1(configuration #2).

Thanks,
Manikanta

[sundaoyu]

Thanks for your support. But how to change [ODMDATA or dtsi or other configs ] to change UPHY config to configuration #2?

[bennaimomer]

Hi Manikanta,
I’m little baffled.
In your first comment you wrote config#2 indeed support C5 and C6.

In the bottom line,
I would like to know if there an option to link PCIe 4lanes AND PCIe 2lanes for both Orin AGX (config#1) AND Xavier AGX without using MUX device.

The only solution I saw is to connect them to UPHY1 and enable C5 and C6 and somhow intervening in the kernel.

Please advice if there any other option.

Thanks in advance,
Omer.

[WayneWWW]

Hi,

Clarification here.

1. We will only support these 3 configs mentioned in hardware design guide. Also, a mixing configuration is not supported. I mean you cannot pick config #1 for uphy0 block and config#2 for uphy1 block. Something like that.

2. Jetpack5.0 DP is only for Devkit to use. As its name, it is just for preview. We don’t support these yet. The document will be ready in jp5.0 GA and we will support these case until then.

[bennaimomer]

Hi,
I understood the configuration issue from the begining, this is not what I’m looking for.
I choose to use config#1 for my design because I need 1 MGBE interface.
I design dual design board which intend to connect to Xavier and Orin AGX modules.

I want to link UPHY1 Lanes 0-3 to m.2 key M socket for NVMe interface and UPHY1 Lanes 4-5 or Lanes 6-7 to m.2 Key B socket.
Is it possible?

Thanks.

[WayneWWW]

If the document told you there is only one controller C5 there , then it cannot be split.

Same rule happens to Xavier AGX/NX.