ORIN AGX PCIE x16 using C5/C7

Is it possible to configure C5/C7 as one pcie x16 using one reference clock and one reset gpio(preferrably C5 rst and refclk)? or do the two busses have to work independently meaning C5 has pexC5refclk and pexC5rst and C7 uses pexC0refclk and pexC0rst? does anyone have an example on the proper configuration?

we have attempted this, but only C5 comes up:

pcie@141a0000 {
compatible = “nvidia,tegra234-pcie”;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) /
<0x00 0x3a000000 0x0 0x00040000>, /
configuration space (256K) /
<0x00 0x3a040000 0x0 0x00040000>, /
iATU_DMA reg space (256K) /
<0x00 0x3a080000 0x0 0x00040000>, /
DBI reg space (256K) /
<0x2b 0x30000000 0x0 0x10000000>; /
ECAM (256MB) */
reg-names = “appl”, “config”, “atu_dma”, “dbi”, “ecam”;

            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            num-lanes = <8>;
            num-viewport = <8>;
            linux,pci-domain = <5>;

            clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
            clock-names = "core";

            resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
                    <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
            reset-names = "apb", "core";

            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
            interrupt-names = "intr", "msi";

            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0>;
            interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

            nvidia,bpmp = <&bpmp 5>;

            nvidia,aspm-cmrt-us = <60>;
            nvidia,aspm-pwr-on-t-us = <20>;
            nvidia,aspm-l0s-entrance-latency-us = <3>;

            bus-range = <0x0 0xff>;

            ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
                    <0x02000000 0x0  0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
                    <0x01000000 0x0  0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */

            interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
                            <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
            interconnect-names = "dma-mem", "write";
            iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
            iommu-map-mask = <0x0>;
            dma-coherent;

            status = "disabled";

            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, <&p2u_nvhs_6>, <&p2u_nvhs_7>;
            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7";

            nvidia,disable-power-down;
    };

C7

    pcie@141e0000 {
            compatible = "nvidia,tegra234-pcie";
            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
            <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
            <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
            <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
            <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
            reg-names = "appl", "config", "atu_dma", "dbi", "ecam";

            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            num-lanes = <8>;
            num-viewport = <8>;
            linux,pci-domain = <5>;

            clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
            clock-names = "core";

            resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
                    <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
            reset-names = "apb", "core";

            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
            interrupt-names = "intr", "msi";

            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0>;
            interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

            nvidia,bpmp = <&bpmp 5>;

            nvidia,aspm-cmrt-us = <60>;
            nvidia,aspm-pwr-on-t-us = <20>;
            nvidia,aspm-l0s-entrance-latency-us = <3>;

            bus-range = <0x0 0xff>;

            ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
                    <0x02000000 0x0  0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
                    <0x01000000 0x0  0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */

            interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
                            <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
            interconnect-names = "dma-mem", "write";
            iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
            iommu-map-mask = <0x0>;
            dma-coherent;

            status = "disabled";

            phys = <&p2u_gbe_0>, <&p2u_gbe_1>, <&p2u_gbe_2>, <&p2u_gbe_3>, <&p2u_gbe_4>, <&p2u_gbe_5>, <&p2u_gbe_6>, <&p2u_gbe_7>;
            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7";

            nvidia,disable-power-down;
    };

Its not possible. PCIe works quite differently on ARM platforms compared to how it does on x86, which usually has blocks of x16 which can be split. The PCIe controllers in the Orin are physically separate IP blocks which only support up to 8 lanes each.
You can see how they are connected in the TRM

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