Orin module Debug mode and NVDBG_SEL, JTAG_TRST_N pins' states in Debug mode

[michael.wu2]

Hello, can you clarify what the module will do in debug mode? We only saw a bit more special coded debug message printed out from the DEBUG_UART3 port when we connect this port from the DevKits.to a computer console.

And what state should carrier card drive to the module’s input pins NVDBG_SEL and JTAG_TRST_N, when in debug mode? (Note: I mean Debug mode, not JTAG Boundary-scan test mode. They are two different modes).

I am afraid I spotted a typo on the Design Guide V1.2 - The DG table 18-2 says JTAG_TRST_N should be left in low-state (module has internal Pulldown) when set the module in Debug mode.
1), This is true for normal operation (to leave JTAG_TRST_N pin low);
2), But in debug mode, ARM processor’s TRSTB pin needs to be released to HIGH state, correct?

Please clarify the pin states:

[michael.wu2]

Good morning. Any updates on this question? Thanks

[Trumany]

Hi, we are checking internally, will update once available, thanks.

[Trumany]

Hi, what “debug mode” do you mean? The table does not mention “debug mode”.

[michael.wu2]

That’s why we have question: what state should signal JTAG_TRST_N be in Debug Mode?
We are looking at Debug Guide V1.2, in which the section 18.2, Figure 18-1 and Note 1 are not clear what state the signal JTAG_TRST_N should be. The note only mentioned NVDGB_SEL should have option to 1V8. See below circled contents.

[sumitg]

Hi,
The below in table “Table 18-1” mentions it to be low.