Orin Nano and tc358743 capture issue

the last column is always determine as board configuration,
please moving this options forward, you may see-also below command-line as an example for disk encryption.
$ sudo ROOTFS_ENC=1 ./tools/kernel_flash/l4t_initrd_flash.sh --showlogs --no-flash --external-device nvme0n1p1 -i ./ekb.key -c ./tools/kernel_flash/flash_l4t_t234_nvme_rootfs_enc.xml --external-only --append --network usb0 jetson-orin-nano-devkit external

Hello Jerry,

I fixed the command to be :

sudo ROOTFS_ENC=1 ./tools/kernel_flash/l4t_initrd_flash.sh --showlogs --no-flash --external-device nvme0n1p1 -i ./ekb.key -c ./tools/kernel_flash/flash_l4t_t234_nvme_rootfs_enc.xml --external-only --append --network usb0 jetson-orin-nano-devkit external

And it appeared to run fine (after installing cryptsetup)

At the completion it says to run the command with “–flash-only” so I ran :

sudo ROOTFS_ENC=1 ./tools/kernel_flash/l4t_initrd_flash.sh --showlogs --flash-only --external-device nvme0n1p1 -i ./ekb.key -c ./tools/kernel_flash/flash_l4t_t234_nvme_rootfs_enc.xml --external-only --append --network usb0 jetson-orin-nano-devkit external

And received this error : (full command line and console logs available if needed)

Waiting for target to boot-up...
Waiting for target to boot-up...
Waiting for target to boot-up...
Waiting for device to expose ssh ......RTNETLINK answers: File exists
RTNETLINK answers: File exists
Waiting for device to expose ssh ...Run command: flash on fc00:1:1:0::2
SSH ready
blockdev: cannot open /dev/mmcblk0boot0: No such file or directory
[ 0]: l4t_flash_from_kernel: Starting to create gpt for external device
Active index file is /mnt/external/flash.idx
Number of lines is 19
max_index=18
writing item=1, 9:0:primary_gpt, 512, 19968, gpt_primary_9_0.bin, 16896, fixed-<reserved>-0, 23bdee126c2bfefb07468c55fee1daa9f8e544b2
Error: Could not stat device /dev/nvme0n1 - No such file or directory.
Flash failure
Cleaning up...

Where is it getting /dev/nvme0n1 from ?

hello anomad,

it’s your external storage.

Hello Jerry,

I see my mistake - I picked “nvme0n1p1” up from a previous example. Will try running w/correct --external-device.

Hello Jerry,

Attempted flash and now the unit only reboots w/a kernel panic.

hello anomad,

it looks you did not update EKS image correctly.
there shows an error to unlock the encrypted partition.
for example, [ 15.583687] ERROR: fail to unlock the encrypted dev /dev/mmcblk1p2.

please refer to this topic for the steps.

Hello Jerry,

Thank you for the link to the signing process - that filled in the blanks in my process to get to where I am successfully booting my signed image. I ran :

sudo ./apply_binaries.sh

# Reconnect Jetson in RM
sudo ./tools/kernel_flash/l4t_initrd_flash.sh --showlogs -p "-c bootloader/t186ref/cfg/flash_t234_qspi.xml" --no-flash --network usb0 jetson-orin-nano-devkit internal 
echo "f0e0d0c0b0a001020304050607080900" > ekb.key

# Reconnect Jetson in RM
sudo ROOTFS_ENC=1 ./tools/kernel_flash/l4t_initrd_flash.sh --showlogs --no-flash --external-device mmcblk1p1 -i ./ekb.key -c ./tools/kernel_flash/flash_l4t_t234_nvme_rootfs_enc.xml --external-only --append --network usb0 jetson-orin-nano-devkit external

# Reconnect Jetson in RM
sudo ./tools/kernel_flash/l4t_initrd_flash.sh --showlogs --network usb0 --flash-only

How do I verify that I am using the updated camera-rtcpu-t234-rce.img ? I created mine on Nov 6.

-rwxrwxr-x 1 parallels parallels 531808 Nov 6 21:08 /home/parallels/nvidia/nvidia_sdk/JetPack_5.1.2_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/camera-rtcpu-t234-rce.img

When I try my capture command

v4l2-ctl --device /dev/video0 --stream-mmap --set-fmt-video=width=1280,height=720,pixelformat=UYVY --stream-to=frame.raw --stream-count=10 --verbose

I am still getting the “vi_capture_control_message: NULL VI channel received” error. Last part of dmesg (let me know if you need the full capture).

[  366.197031] NVRM rpcRmApiControl_dce: NVRM_RPC_DCE: Failed RM ctrl call cmd:0x731341 result 0xffff:
[ 5666.699172] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffcf0800, fsynr=0xb0003, cbfrsynra=0x405, cb=3
[ 5666.714752] mc-err: (255) csr_pcie1r: EMEM address decode error
[ 5666.721198] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[ 5666.729509] mc-err:   secure: yes, access-type: read
[16628.554088] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffd2c000, fsynr=0xb0003, cbfrsynra=0x5, cb=3
[16628.569402] mc-err: (255) csr_pcie1r: EMEM address decode error
[16628.575787] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[16628.584060] mc-err:   secure: yes, access-type: read
[22436.182186] tc358743 9-000f: tc358743_set_pll:
[22436.186916] tc358743 9-000f: tc358743_set_csi_color_space: YCbCr 422 16-bit
[22436.188657] tc358743 9-000f: tc358743_g_input_status: status = 0x0
[22436.189048] tc358743 9-000f:   jc - FOUND signal and sync!
[22436.191175] tc358743 9-000f: tc358743_query_dv_timings: 1280x720p60.00 (1650x750)
[22436.191204] tc358743 9-000f: tc358743_s_dv_timings: 1280x720p60.00 (1650x750)
[22436.192134] tc358743 9-000f: tc358743_set_pll:
[22436.213817] bwmgr API not supported
[22438.819386] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[22438.832141] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[22438.842582] (NULL device *): vi_capture_control_message: NULL VI channel received
[22438.850351] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[22438.861068] (NULL device *): vi_capture_control_message: NULL VI channel received
[22438.868809] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[22438.879715] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[22441.411060] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[22441.420211] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[22441.430774] (NULL device *): vi_capture_control_message: NULL VI channel received
[22441.438526] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[22441.449187] (NULL device *): vi_capture_control_message: NULL VI channel received
[22441.456915] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[22441.467863] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[22441.485153] bwmgr API not supported
[36032.217309] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffd64000, fsynr=0x380003, cbfrsynra=0x805, cb=3
[36032.233526] mc-err: (255) csr_pcie1r: EMEM address decode error
[36032.239758] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[36032.248254] mc-err:   secure: yes, access-type: read
[73894.670859] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffd32000, fsynr=0x380003, cbfrsynra=0x5, cb=3
[73894.683315] mc-err: (255) csr_pcie1r: EMEM address decode error
[73894.689570] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[73894.697836] mc-err:   secure: yes, access-type: read
[77674.572296] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffc29000, fsynr=0xb0003, cbfrsynra=0x805, cb=3
[77674.587800] mc-err: Too many MC errors; throttling prints
[86683.434131] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffa5e000, fsynr=0x380003, cbfrsynra=0x805, cb=3
[86683.446907] mc-err: (255) csr_pcie1r: EMEM address decode error
[86683.453054] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[86683.461309] mc-err:   secure: yes, access-type: read
[87376.443257] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffa9e800, fsynr=0xb0003, cbfrsynra=0x805, cb=3
[87376.458773] mc-err: (255) csr_pcie1r: EMEM address decode error
[87376.465119] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[87376.473459] mc-err:   secure: yes, access-type: read
[91408.406035] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffc0e800, fsynr=0x380003, cbfrsynra=0xc05, cb=3
[91408.418818] mc-err: (255) csr_pcie1r: EMEM address decode error
[91408.425072] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[91408.433415] mc-err:   secure: yes, access-type: read
[105016.145648] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffc35800, fsynr=0xb0003, cbfrsynra=0x405, cb=3
[105016.161176] mc-err: (255) csr_pcie1r: EMEM address decode error
[105016.167673] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[105016.176012] mc-err:   secure: yes, access-type: read
[127191.789243] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffa7c800, fsynr=0x380003, cbfrsynra=0x805, cb=3
[127191.801862] mc-err: Too many MC errors; throttling prints
[128514.770093] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffb8d000, fsynr=0x380003, cbfrsynra=0x405, cb=3
[128514.782797] mc-err: (255) csr_pcie1r: EMEM address decode error
[128514.789096] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[128514.797437] mc-err:   secure: yes, access-type: read
[130278.768133] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffb48000, fsynr=0x380003, cbfrsynra=0x405, cb=3
[130278.780828] mc-err: (255) csr_pcie1r: EMEM address decode error
[130278.787237] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[130278.795587] mc-err:   secure: yes, access-type: read
[163227.223593] arm-smmu 8000000.iommu: Unhandled context fault: fsr=0x80000402, iova=0xffc95800, fsynr=0x380003, cbfrsynra=0x405, cb=3
[163227.236281] mc-err: (255) csr_pcie1r: EMEM address decode error
[163227.242599] mc-err:   status = 0x200640da; hi_addr_reg = 0x000000ff addr = 0xffffffff00
[163227.250932] mc-err:   secure: yes, access-type: read
[179485.959015] tc358743 9-000f: tc358743_set_pll:
[179485.963541] tc358743 9-000f: tc358743_set_csi_color_space: YCbCr 422 16-bit
[179485.965044] tc358743 9-000f: tc358743_g_input_status: status = 0x0
[179485.965424] tc358743 9-000f:   jc - FOUND signal and sync!
[179485.967390] tc358743 9-000f: tc358743_query_dv_timings: 1280x720p60.00 (1650x750)
[179485.986723] bwmgr API not supported
[179488.519417] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[179488.532364] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[179488.542569] (NULL device *): vi_capture_control_message: NULL VI channel received
[179488.550437] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[179488.561237] (NULL device *): vi_capture_control_message: NULL VI channel received
[179488.569066] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[179488.580044] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[179491.111393] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[179491.120642] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[179491.130570] (NULL device *): vi_capture_control_message: NULL VI channel received
[179491.138424] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[179491.149198] (NULL device *): vi_capture_control_message: NULL VI channel received
[179491.157133] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[179491.168082] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

Thank you

hello anomad,

you may review the checksum in the booting messages.
for example,
on r35.4.1/AGX-Orin, the checksum of default camera firmware is.
tegra186-cam-rtcpu bc00000.rtcpu: firmware version cpu=rce cmd=6 sha1=8676d22a01443bdbc66581b7dde3b6d6828cc925

here’s checksum after you update camera firmware with deskew fix.
tegra186-cam-rtcpu bc00000.rtcpu: firmware version cpu=rce cmd=6 sha1=73154acbae92fa621c3d5e1b2a6e10f1075059aa

Hello Jerry,

From dmesg :

root@orindev:/var/log# dmesg | grep tegra186-cam-rtcpu
[    5.809726] tegra186-cam-rtcpu bc00000.rtcpu: Adding to iommu group 7
[    5.826924] tegra186-cam-rtcpu bc00000.rtcpu: Trace buffer configured at IOVA=0xbff00000
[    5.944255] tegra186-cam-rtcpu bc00000.rtcpu: using cam RTCPU IRQ (111)
[    5.951082] tegra186-cam-rtcpu bc00000.rtcpu: tegra_camrtc_mon_create is successful
[    5.960878] tegra186-cam-rtcpu bc00000.rtcpu: firmware version cpu=rce cmd=6 sha1=73154acbae92fa621c3d5e1b2a6e10f1075059aa

This verifies the patch is active, but I still have the same error when trying to capture video. What information can I provide to assist in troubleshooting ?

hello anomad,

please check VI tracing logs,
do you still see the same PHY interrupts as mentioned in comment #3?

Hello Jerry,

I appear to have the same results :

# tracer: nop
#
# entries-in-buffer/entries-written: 232841/232841   #P:6
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
        v4l2-ctl-26454   [005] .... 260029.795448: tegra_channel_open: vi-output, tc358743 9-000f
        v4l2-ctl-26454   [005] .... 260029.811967: tegra_channel_set_power: tc358743 9-000f : 0x1
        v4l2-ctl-26454   [005] .... 260029.811970: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-26454   [005] .... 260029.811973: csi_s_power: enable : 0x1
        v4l2-ctl-26454   [005] .... 260029.812637: tegra_channel_capture_setup: vnc_id 0 W 1280 H 720 fmt 13
        v4l2-ctl-26454   [005] .... 260029.819835: tegra_channel_set_stream: enable : 0x1
        v4l2-ctl-26454   [005] .... 260029.821580: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-26454   [005] .... 260029.821582: csi_s_stream: enable : 0x1
        v4l2-ctl-26454   [005] .... 260029.821965: tegra_channel_set_stream: tc358743 9-000f : 0x1
     kworker/4:2-22515   [004] .... 260029.854450: rtcpu_string: tstamp:8130911051946 id:0x04010000 str:"VM0 activating."
     kworker/4:2-22515   [004] .... 260029.854455: rtcpu_nvcsi_intr: tstamp:8130911285595 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x02000000
     kworker/4:2-22515   [004] .... 260029.854455: rtcpu_nvcsi_intr: tstamp:8130911286152 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000004
     kworker/4:2-22515   [004] .... 260029.854456: rtcpu_nvcsi_intr: tstamp:8130911286760 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854456: rtcpu_nvcsi_intr: tstamp:8130911287315 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854456: rtcpu_nvcsi_intr: tstamp:8130911287897 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854457: rtcpu_nvcsi_intr: tstamp:8130911288462 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854457: rtcpu_nvcsi_intr: tstamp:8130911289039 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854457: rtcpu_nvcsi_intr: tstamp:8130911289693 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854457: rtcpu_nvcsi_intr: tstamp:8130911290388 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854458: rtcpu_nvcsi_intr: tstamp:8130911291083 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854458: rtcpu_nvcsi_intr: tstamp:8130911291777 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854458: rtcpu_nvcsi_intr: tstamp:8130911292473 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854459: rtcpu_nvcsi_intr: tstamp:8130911293168 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854459: rtcpu_nvcsi_intr: tstamp:8130911293862 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854459: rtcpu_nvcsi_intr: tstamp:8130911294558 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854460: rtcpu_nvcsi_intr: tstamp:8130911295254 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854460: rtcpu_nvcsi_intr: tstamp:8130911295949 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854460: rtcpu_nvcsi_intr: tstamp:8130911296642 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854460: rtcpu_nvcsi_intr: tstamp:8130911297337 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854461: rtcpu_nvcsi_intr: tstamp:8130911298032 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854461: rtcpu_nvcsi_intr: tstamp:8130911298729 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/4:2-22515   [004] .... 260029.854461: rtcpu_nvcsi_intr: tstamp:8130911299426 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004

hello anomad,

you may examine with your sensor configuration.

Hello Jerry,

I’m not sure what you are suggesting I do next. Can you be more specific?

Does my output mean the patch did not work?

Thank you,

please see-also Topic 264645 for some modifications.

Hello Jerry,

I’m not sure what the takeaway is from the topic you posted.

The user claimed the Jetson can only output 24M clock and not the 27M clock the tc358743 needs. Is that a correct statement? We have used the tc358743’s on a Jetson Nano and Xavier without any issues, but the Orin seems to be configured completely different.

He goes on to describe changes in vi5/csi5 code to make his board work (but offers no examples), but ShaneCCC says:

Orin is vi5/csi5
Sorry there’s no document for it.

so that isn’t really helpful either.

It appears from other posts that using a tc358743 to convert HDMI to CSI on the Orin is possible, but after this whole process of rebuilding everything to be signed so I could use the patch you provided I’m beginning to wonder.

What is the next step to troubleshoot?

Thank you

hello anomad,

you may refer to the thread to review those sensor operations.
please also dig into csi5_fops.c of the csi5_stream_set_config function to add necessary properties as mentioned.

BTW, did you have other platform to verify this TC358743? did it output frames correctly?

I am also attempting to use the TC358743 on the Orin Nano, and having more or less the same issues.

My process started with an existing device tree and driver for the Xavier NX. The driver needed a few small changes, mainly to support the replacement of v4l2-of with v4l2-fwnode in Linux 5.x. The device tree required some changes that I’m not entirely certain about, mostly because writing device trees is entirely new to me, but does at least get the /dev/video0 node to show up.

The end result is extremely similar to the existing issues posted in this thread. I can see the video device and query information about it, but attempting to capture video results in the same sequence of VI channel errors.

[  492.169687] (NULL device *): vi_capture_control_message: NULL VI channel received
[  492.177427] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=1, csi_port=1
[  492.188116] (NULL device *): vi_capture_control_message: NULL VI channel received
[  492.195843] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 1 vc- 0
[  492.206849] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

My debug trace appears to be slightly different.

# tracer: nop
#
# entries-in-buffer/entries-written: 454993/454993   #P:6
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
     kworker/3:3-126     [003] ....    78.440626: rtcpu_string: tstamp:3296073693 id:0x04010000 str:"VM0 deactivating."
  gst-launch-1.0-2576    [002] ....    80.454091: tegra_channel_open: vi-output, tc358743 2-000f
  gst-launch-1.0-2576    [002] ....    80.454111: tegra_channel_close: vi-output, tc358743 2-000f
  gst-launch-1.0-2576    [002] ....    81.103817: tegra_channel_open: vi-output, tc358743 2-000f
    v4l2src0:src-2578    [005] ....    81.173413: tegra_channel_set_power: tc358743 2-000f : 0x1
    v4l2src0:src-2578    [005] ....    81.173417: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
    v4l2src0:src-2578    [005] ....    81.173419: csi_s_power: enable : 0x1
    v4l2src0:src-2578    [005] ....    81.174050: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
    v4l2src0:src-2578    [005] ....    81.180990: tegra_channel_set_stream: enable : 0x1
    v4l2src0:src-2578    [005] ....    81.182966: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
    v4l2src0:src-2578    [005] ....    81.182968: csi_s_stream: enable : 0x1
    v4l2src0:src-2578    [005] ....    81.183349: tegra_channel_set_stream: tc358743 2-000f : 0x1
     kworker/3:3-126     [003] ....    81.184449: rtcpu_string: tstamp:3383286252 id:0x04010000 str:"VM0 activating."
     kworker/3:3-126     [003] ....    81.240435: rtcpu_vinotify_event: tstamp:3383742556 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:108269461856 data:0x399d580010000000
     kworker/3:3-126     [003] ....    81.240438: rtcpu_vinotify_event: tstamp:3383742822 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:108269471616 data:0x0000000031000001
     kworker/3:3-126     [003] ....    81.240439: rtcpu_vinotify_event: tstamp:3383743116 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:108269563232 data:0x399d550010000000
     kworker/3:3-126     [003] ....    81.240439: rtcpu_vinotify_event: tstamp:3383743372 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:108269573088 data:0x0000000031000002
     kworker/3:3-126     [003] ....    81.240441: rtcpu_nvcsi_intr: tstamp:3383799480 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x14000040
     kworker/3:3-126     [003] ....    81.240442: rtcpu_nvcsi_intr: tstamp:3383800039 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000040
...
...
...
     kworker/3:3-126     [003] ....    81.240700: rtcpu_nvcsi_intr: tstamp:3384256831 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000040
     kworker/3:3-126     [003] ....    81.240700: rtcpu_nvcsi_intr: tstamp:3384259532 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x04000000
     kworker/3:3-126     [003] ....    81.240700: rtcpu_nvcsi_intr: tstamp:3384260446 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x14000000
     kworker/3:3-126     [003] ....    81.240701: rtcpu_nvcsi_intr: tstamp:3384278046 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x10000040

At this point I’m not sure what path to take in order to debug this, or what further changes need to be made to support the Orin.

I currently have this module working on a Xavier NX with the exact driver and device tree I referenced from GitHub above. It doesn’t need any changes to csi[N]_fops.c to get it working, nor does it use the tegracam API. Topic 264645 suggests the tegracam API is necessary to get it working with the Orin, but the TC358840 driver at kernel/nvidia/drivers/media/i2c/tc358840.c in the Jetson Linux 35.4.1 source doesn’t seem to use the tegracam API either, so I wonder if that is true. In any case, the other thread is extremely unclear about how the problem was solved, so it’s hard to derive any useful information from it.

I’ve put my device tree below for reference. I will also add the WIP driver. It’s a bit of a mess though, being a combination of the driver from GitHub and tests from using the original TC358743 driver in the Linux kernel source as a reference.

tegra234-orin-tc358743.dtsi

#include <dt-bindings/media/camera.h>
#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/clock/tegra234-clock.h>

#define CAM0_PWDN	TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_PWDN	TEGRA234_MAIN_GPIO(AC, 0)
#define CAM_I2C_MUX TEGRA234_AON_GPIO(CC, 3)


/{
	gpio@2200000 {
		//#gpio-cells = <2>;
		camera-control-output-low {
			gpio-hog;
			output-low;
			gpios = < CAM0_PWDN 0 >;
			label = "cam0-pwdn";
		};
	};

	tegra-capture-vi {
		num-channels = <1>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			tc358743_vi_port2: port@0 {
				status = "okay";
				reg = <0>;
				tc358743_vi_in0: endpoint {
					status = "okay";
					port-index = <0>;
					csi-port = <0>;  /* CSI-C */
					bus-width = <2>; /* Use CSI-CD*/
					remote-endpoint = <&tc358743_csi_out0>;
				};
			};
		};
	};

	host1x@13e00000 {
		nvcsi@15a00000 {
			num-channels = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			channel@0 {
				reg = <0>;
				status = "okay";
					ports {
						#address-cells = <1>;
						#size-cells = <0>;
						port@0 {
							status = "okay";
							reg = <0>;
							tc358743_csi_in0: endpoint@0 {
								status = "okay";
								port-index = <0>;
								csi-port = <0>;
								bus-width = <2>;
								remote-endpoint = <&tc358743_out0>;
							};
						};
						port@1 {
							status = "okay";
							reg = <1>;
							tc358743_csi_out0: endpoint@1 {
								status = "okay";
								remote-endpoint = <&tc358743_vi_in0>;
						};
					};
				};
			};
		};
	};

	i2c@3180000 {  /* I2C_0, "adapter" 0 */
		status = "okay";
		#address-cells = <1>;
		#size-cells = <0>;
		tc358743@0f {
			status = "okay";
			compatible = "tc358743";
			reg = <0x0f>; /* (normal = address not shifted) */

			devnode = "video0";

			// Trying to make sense of these reference clocks
			clocks = <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>;

			//clock-names = “extperiph1”, “pllp_grtba”;
			clock-names = "extperiph1";
			clock-frequency = <27000000>;

			mclk = "cam_mclk1";

		   	//reset-gpios = <&gpio 151 0>; // EDO commented out to test
			reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;

			refclk_hz = <27000000>;  // refclk_hz -> regclk

			//interrupt-parent = <&gpio>;
			interrupt-parent = <&tegra_main_gpio>;

			interrupts = <TEGRA234_MAIN_GPIO(H, 0) GPIO_ACTIVE_HIGH>;

			/* Physical dimensions of sensor */
			physical_w = "4.713";
			physical_h = "3.494";

			/* Sensor Model */
			sensor_model = "tc358743";

			ddc5v_delay = <2>;
			enable_hdcp = "false";
			lineinitcnt = <0xe80>;
			lptxtimecnt = <0x003>;
			tclk_headercnt = <0x1403>;
			tclk_trailcnt = <0x00>;
			ths_headercnt = <0x0103>;
			twakeup = <0x4882>;
			tclk_postcnt = <0x008>;
			ths_trailcnt = <0x02>;
			hstxvregcnt = <0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					tc358743_out0: endpoint {
						port-index = <0>; /* CSI B */
						bus-width = <2>; /* Use CSI-B only */
						data-lanes = <1 2>;
						clock-lanes = <0>;
						clock-noncontinuous;
						link-frequencies = /bits/ 64 <297000000>;
						remote-endpoint = <&tc358743_csi_in0>;
					};
				};
			};
		};
	};

	tcp: tegra-camera-platform {
		status = "okay";
		compatible = "nvidia, tegra-camera-platform";
		num_csi_lanes = <2>;
		max_lane_speed = <1500000>;
		min_bits_per_pixel = <16>;
		vi_peak_byte_per_pixel = <2>;
		vi_bw_margin_pct = <25>;
		max_pixel_rate = <430000>;  //408000  this is related to the capped VI's max BW  max_pixel_rate / 0.4 = capped VI BW  
		isp_peak_byte_per_pixel = <2>;
		isp_bw_margin_pct = <25>;

		/**
		* The general guideline for naming badge_info contains 3 parts, and is as follows,
		* The first part is the camera_board_id for the module; if the module is in a FFD
		* platform, then use the platform name for this part.
		* The second part contains the position of the module, ex. “rear” or “front”.
		* The third part contains the last 6 characters of a part number which is found
		* in the module's specsheet from the vender.
		*/
		modules {
			module0 {
				status = "okay";
				badge = "tc358743_top_i2c0_cd";
				position = "top";
				orientation = "3";
				drivernode0 {
					status = "okay";
					/* Declare PCL support driver (classically known as guid)  */
					pcl_id = "v4l2_sensor";
					/* Driver's v4l2 device name */
					devname = "tc358743 0-000f";
					/* Declare the device-tree hierarchy to driver instance */
					proc-device-tree = "/proc/device-tree/i2c@3180000/tc358743@0f";
				};
			};
		};
	};
};

tc358743.c

/*
* References (c = chapter, p = page):
* REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
* REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
*/
#define DEBUG
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/of_graph.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/hdmi.h>
#include <media/cec.h>
#include <media/v4l2-dv-timings.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#include <media/camera_common.h>
//#include <media/i2c/tc358743.h>
#include "tc358743.h"

#include <dt-bindings/gpio/tegra-gpio.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/gpio.h>
#include <linux/module.h>

#include <linux/seq_file.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>

#include <linux/i2c-dev.h>
#include <linux/fs.h>

// #include <media/v4l2-chip-ident.h>
#include <media/tegra-v4l2-camera.h>
#include <media/camera_common.h>
//#include <media/soc_camera.h>

#include "tc358743_regs.h"

/* RGB ouput selection */
// #define TC358743_VOUT_RGB

static int debug = 3;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-3)");

MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
MODULE_LICENSE("GPL");

/* mode */
enum {
	tc358743_MODE_1280X720,
	tc358743_MODE_1920X1080,
};

/* frame rate */
static const int tc358743_30fps[] = {
	30,
};
static const int tc358743_30_60fps[] = {
	30,
	50,
	60,
};
static const int tc358743_50fps[] = {
	50,
};

/* frame format */
static const struct camera_common_frmfmt tc358743_frmfmt[] = {
	{{1280,  720}, tc358743_30_60fps, 3, 0, tc358743_MODE_1280X720},
	{{1920, 1080}, tc358743_30_60fps, 3, 0, tc358743_MODE_1920X1080},
};

// static const struct camera_common_colorfmt tc358743_color_fmts[] = {
// 	{
// 		MEDIA_BUS_FMT_SRGGB12_1X12,
// 		V4L2_COLORSPACE_SRGB,
// 		V4L2_PIX_FMT_SRGGB12,
// 	},
// 	{
// 		MEDIA_BUS_FMT_UYVY8_1X16,
// 		V4L2_COLORSPACE_SRGB,
// 		V4L2_PIX_FMT_UYVY,
// 	},
// };

#define EDID_NUM_BLOCKS_MAX 8
#define EDID_BLOCK_SIZE 128
static u8 edid[] = {

// #ifdef TC358743_VOUT_RGB
	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
	0x50, 0x21, 0x9C, 0x27, 0x00, 0x00, 0x00, 0x00,
	0x19, 0x12, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
	0x0E, 0x00, 0xB2, 0xA0, 0x57, 0x49, 0x9B, 0x26,
	0x10, 0x48, 0x4F, 0x2F, 0xCF, 0x00, 0x31, 0x59,
	0x45, 0x59, 0x61, 0x59, 0x81, 0x99, 0x01, 0x01,
	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
	0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
	0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E,
	0x00, 0x00, 0x00, 0xFD, 0x00, 0x31, 0x55, 0x18,
	0x5E, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20,
	0x20, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
	0x6F, 0x73, 0x68, 0x69, 0x62, 0x61, 0x2D, 0x48,
	0x32, 0x43, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc3,
	0x02, 0x03, 0x1a, 0xc0, 0x48, 0xa2, 0x10, 0x04,
	0x02, 0x01, 0x21, 0x14, 0x13, 0x23, 0x09, 0x07,
	0x07, 0x65, 0x03, 0x0c, 0x00, 0x10, 0x00, 0xe2,
	0x00, 0x2a, 0x01, 0x1d, 0x00, 0x80, 0x51, 0xd0,
	0x1c, 0x20, 0x40, 0x80, 0x35, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x1e, 0x8c, 0x0a, 0xd0, 0x8a,
	0x20, 0xe0, 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7
// #else
	//0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
	//0x52, 0x62, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88,
	//0x1C, 0x15, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
	//0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
	//0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
	//0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
	//0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
	//0x80, 0xD0, 0x72, 0x38, 0x2D, 0x40, 0x10, 0x2C,
	//0x45, 0x80, 0x66, 0x4C, 0x00, 0x00, 0x00, 0x1E,
	//0x01, 0x1D, 0x00, 0xBC, 0x52, 0xD0, 0x1E, 0x20,
	//0xB8, 0x28, 0x55, 0x40, 0x66, 0x4C, 0x00, 0x00,
	//0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
	//0x6F, 0x73, 0x68, 0x69, 0x62, 0x61, 0x2D, 0x48,
	//0x32, 0x43, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
	//0x00, 0x14, 0x78, 0x01, 0xFF, 0x10, 0x00, 0x0A,
	//0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0xBA,
	//0x02, 0x03, 0x1A, 0x71, 0x47, 0x9F, 0x13, 0x22,
	//0x1F, 0x02, 0x11, 0x1F, 0x23, 0x09, 0x07, 0x01,
	//0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
	//0x10, 0x00, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38,
	//0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0x66, 0x4C,
	//0x00, 0x00, 0x00, 0x1E, 0x02, 0x3A, 0x80, 0xD0,
	//0x72, 0x38, 0x2D, 0x40, 0x10, 0x2C, 0x45, 0x80,
	//0x66, 0x4C, 0x00, 0x00, 0x00, 0x1E, 0x8C, 0x0A,
	//0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E,
	//0x96, 0x00, 0x66, 0x4C, 0x00, 0x00, 0x00, 0x18,
	//0x8C, 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20,
	//0x0C, 0x40, 0x55, 0x00, 0x66, 0x4C, 0x00, 0x00,
	//0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	//0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	//0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	//0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
// #endif
};
/* Max transfer size done by I2C transfer functions */
#define I2C_MAX_XFER_SIZE  (EDID_NUM_BLOCKS_MAX * EDID_BLOCK_SIZE + 2)
//#define I2C_MAX_XFER_SIZE  (EDID_BLOCK_SIZE + 2)

#define POLL_INTERVAL_CEC_MS	10
#define POLL_INTERVAL_MS	1000

static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
	.type = V4L2_DV_BT_656_1120,
	/* keep this initialization for compatibility with GCC < 4.4.6 */
	.reserved = { 0 },
	/* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
	//V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
	V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
			V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
			V4L2_DV_BT_CAP_PROGRESSIVE |
			V4L2_DV_BT_CAP_REDUCED_BLANKING |
			V4L2_DV_BT_CAP_CUSTOM)
};

struct tc358743_state {
	struct tc358743_platform_data pdata;
	// struct v4l2_fwnode_bus_mipi_csi2 bus;
	struct v4l2_subdev sd;
	struct media_pad pad;
	struct v4l2_ctrl_handler hdl;
	struct i2c_client *i2c_client;
    struct regmap *regmap;
	/* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
	struct mutex confctl_mutex;

	/* controls */
	struct v4l2_ctrl *detect_tx_5v_ctrl;
	struct v4l2_ctrl *audio_sampling_rate_ctrl;
	struct v4l2_ctrl *audio_present_ctrl;

	/* work queues */
	struct workqueue_struct *work_queues;
	struct delayed_work delayed_work_enable_hotplug;

	struct timer_list timer;
	struct work_struct work_i2c_poll;

	/* edid  */
	u8 edid_blocks_written;

	/* used by i2c_wr() */
	u8 wr_data[I2C_MAX_XFER_SIZE];

	struct v4l2_dv_timings timings;
	u32 mbus_fmt_code;
	u8 csi_lanes_in_use;

	struct gpio_desc *reset_gpio;

	struct cec_adapter *cec_adap;
};

static int tc358743_log_status(struct v4l2_subdev *sd);
static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
		bool cable_connected);
static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);

static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
{
	return container_of(sd, struct tc358743_state, sd);
}

/* --------------- I2C --------------- */

static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
{
	struct tc358743_state *state = to_state(sd);
	struct i2c_client *client = state->i2c_client;
	int err;
	u8 buf[2] = { reg >> 8, reg & 0xff };
	struct i2c_msg msgs[] = {
		{
			.addr = client->addr,
			.flags = 0,
			.len = 2,
			.buf = buf,
		},
		{
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = n,
			.buf = values,
		},
	};

	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
	if (err != ARRAY_SIZE(msgs)) {
		v4l2_err(sd, "%s: #### reading register0x%x from0x%x failed\n",
				__func__, reg, client->addr);
		return -1;
	}
	//udelay(10);
	return 0;
}

static int i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
{
	struct tc358743_state *state = to_state(sd);
	struct i2c_client *client = state->i2c_client;
	int err, i;
	struct i2c_msg msg;
	u8 *data = state->wr_data;

	if ((2 + n) > sizeof(state->wr_data)){
		v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
			  reg, 2 + n);
		return -1;
	}

	msg.addr = client->addr;
	msg.buf = data;
	msg.len = 2 + n;
	msg.flags = 0;

	data[0] = reg >> 8;
	data[1] = reg & 0xff;

	for (i = 0; i < n; i++)
		data[2 + i] = values[i];

	err = i2c_transfer(client->adapter, &msg, 1);
	if (err != 1) {
		v4l2_err(sd, "%s: writing register0x%x from0x%x failed\n",
				__func__, reg, client->addr);
		return -1;
	}
	return 0;
}

static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
{
	__le32 val = 0;

	i2c_rd(sd, reg, (u8 __force *)&val, n);

	return le32_to_cpu(val);
}

static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
{
	__le32 raw = cpu_to_le32(val);

	i2c_wr(sd, reg, (u8 __force *)&raw, n);
}

static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
{
	return i2c_rdreg(sd, reg, 1);
}

static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
{
	i2c_wrreg(sd, reg, val, 1);
}

static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
		u8 mask, u8 val)
{
	i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
}

static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
{
	return i2c_rdreg(sd, reg, 2);
}

static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
{
	i2c_wrreg(sd, reg, val, 2);
}

static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
{
	i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
}

static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
{
	return i2c_rdreg(sd, reg, 4);
}

static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
{
	i2c_wrreg(sd, reg, val, 4);
}

/* --------------- STATUS --------------- */

static inline bool is_hdmi(struct v4l2_subdev *sd)
{
	return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
}

static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
{
	return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
}

static inline bool no_signal(struct v4l2_subdev *sd)
{
	return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
}

static inline bool no_sync(struct v4l2_subdev *sd)
{
	return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
}

static inline bool audio_present(struct v4l2_subdev *sd)
{
	return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
}

static int get_audio_sampling_rate(struct v4l2_subdev *sd)
{
	static const int code_to_rate[] = {
		44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
		88200, 768000, 96000, 705600, 176400, 0, 192000, 0
	};

	/* Register FS_SET is not cleared when the cable is disconnected */
	if (no_signal(sd))
		return 0;

	return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
}

/* --------------- TIMINGS --------------- */

static inline unsigned fps(const struct v4l2_bt_timings *t)
{
	if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
		return 0;

	return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
			V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
}

static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
				     struct v4l2_dv_timings *timings)
{
	struct v4l2_bt_timings *bt = &timings->bt;
	unsigned width, height, frame_width, frame_height, frame_interval, fps;

	memset(timings, 0, sizeof(struct v4l2_dv_timings));

	if (no_signal(sd)) {
		v4l2_info(sd, "%s: no valid signal\n", __func__);
		return -ENOLINK;
	}
	if (no_sync(sd)) {
		v4l2_info(sd, "%s: no sync on signal\n", __func__);
		return -ENOLCK;
	}

	timings->type = V4L2_DV_BT_656_1120;
	bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
		V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;

	width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
		i2c_rd8(sd, DE_WIDTH_H_LO);
	height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
		i2c_rd8(sd, DE_WIDTH_V_LO);
	frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
		i2c_rd8(sd, H_SIZE_LO);
	frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
		i2c_rd8(sd, V_SIZE_LO)) / 2;
	/* frame interval in milliseconds * 10
	 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
	frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
		i2c_rd8(sd, FV_CNT_LO);
	fps = (frame_interval > 0) ?
		DIV_ROUND_CLOSEST(10000, frame_interval) : 0;

	bt->width = width;
	bt->height = height;
	bt->vsync = frame_height - height;
	bt->hsync = frame_width - width;
	bt->pixelclock = frame_width * frame_height * fps;
	if (bt->interlaced == V4L2_DV_INTERLACED) {
		bt->height *= 2;
		bt->il_vsync = bt->vsync + 1;
		bt->pixelclock /= 2;
	}
	v4l2_info(sd,"%d:%s: width %d heigh %d interlaced %d\n",__LINE__,__FUNCTION__,
	        bt->width,
	        bt->height,
	        bt->interlaced);
	return 0;
}
/* --------------- HOTPLUG / HDCP / EDID --------------- */

static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
{
	struct delayed_work *dwork = to_delayed_work(work);
	struct tc358743_state *state = container_of(dwork,
			struct tc358743_state, delayed_work_enable_hotplug);
	struct v4l2_subdev *sd = &state->sd;

	v4l2_info(sd, "%s:\n", __func__);


	i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
	/*hainh
	i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_CTL0, MASK_HPD_CTL0);
	*/
}

static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
{
	v4l2_info(sd, "%s: %s\n", __func__, enable ?
				"enable" : "disable");

	if (enable) {
		i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);

		i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);

		i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
				MASK_AUTH_UNAUTH_SEL_16_FRAMES |
				MASK_AUTH_UNAUTH_AUTO);

		i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
				SET_AUTO_P3_RESET_FRAMES(0x0f));
	} else {
		i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
				MASK_MANUAL_AUTHENTICATION);
	}
}

static void tc358743_disable_edid(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	v4l2_info(sd, "%s:\n", __func__);

	cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);

	/* DDC access to EDID is also disabled when hotplug is disabled. See
	 * register DDC_CTL */
	i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
}

static void tc358743_enable_edid(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	v4l2_info(sd, "%s\n", __func__);
	if (state->edid_blocks_written == 0) {
		v4l2_info(sd, "%s: no EDID -> no hotplug\n", __func__);
		tc358743_s_ctrl_detect_tx_5v(sd);
		return;
	}

	v4l2_info(sd, "%s:\n", __func__);

	/* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
	 * hotplug is enabled. See register DDC_CTL */
	queue_delayed_work(state->work_queues,
			           &state->delayed_work_enable_hotplug, HZ / 10);

	tc358743_enable_interrupts(sd, true);
	tc358743_s_ctrl_detect_tx_5v(sd);
	v4l2_info(sd, "%s completed successfully", __FUNCTION__);
}

static void tc358743_erase_bksv(struct v4l2_subdev *sd)
{
	int i;

	for (i = 0; i < 5; i++)
		i2c_wr8(sd, BKSV + i, 0);
}

/* --------------- AVI infoframe --------------- */

static void print_avi_infoframe(struct v4l2_subdev *sd)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct device *dev = &client->dev;
	union hdmi_infoframe frame;
	u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];

	if (!is_hdmi(sd)) {
		v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
		return;
	}

	i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));

	if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
		v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
		return;
	}

	hdmi_infoframe_log(KERN_INFO, dev, &frame);
}

/* --------------- CTRLS --------------- */

static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
			tx_5v_power_present(sd));
}

static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
			get_audio_sampling_rate(sd));
}

static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, audio_present(sd));
}

static int tc358743_update_controls(struct v4l2_subdev *sd)
{
	int ret = 0;

	ret |= tc358743_s_ctrl_detect_tx_5v(sd);
	ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
	ret |= tc358743_s_ctrl_audio_present(sd);

	return ret;
}

static int tc358743_get_edid(struct v4l2_subdev *sd){
 	//static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 	//int i = 0;
	u8 edid_read[256];
	int result = 0;
	u32 n = sizeof(edid_read);

	result = i2c_rd(sd,EDID_RAM,edid_read,n);
	v4l2_info(sd, "%s i2c_rd return %d\r\n",__func__,result);
	//for(i = 0; i< n;i++)
	//	printk("%02x ",edid_read[i]);
	v4l2_info(sd, "%s done\r\n",__func__);
	return 0;
}

/* --------------- INIT --------------- */

static void tc358743_reset_phy(struct v4l2_subdev *sd)
{
	v4l2_info(sd, "%s:\n", __func__);

	i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
	i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
}

static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
{
	u16 sysctl = i2c_rd16(sd, SYSCTL);

	i2c_wr16(sd, SYSCTL, sysctl | mask);
	i2c_wr16(sd, SYSCTL, sysctl & ~mask);
}

static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
{
	i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, enable ? MASK_SLEEP : 0);
}

static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
{
	struct tc358743_state *state = to_state(sd);

	v4l2_info(sd, "%s: %sable\n",	__func__, enable ? "en" : "dis");

	if (enable) {
		/* It is critical for CSI receiver to see lane transition
		 * LP11->HS. Set to non-continuous mode to enable clock lane
		 * LP11 state. */
		i2c_wr32(sd, TXOPTIONCNTRL, 0);
		/* Set to continuous mode to trigger LP11->HS transition */
		i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
		/* Unmute video */
		i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
	} else {
		/* Mute video so that all data lanes go to LSP11 state.
		 * No data is output to CSI Tx block. */
		i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
	}

	mutex_lock(&state->confctl_mutex);
	i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
			enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
	mutex_unlock(&state->confctl_mutex);
	v4l2_info(sd,"%d:%s: end\n",__LINE__,__FUNCTION__);
	if (enable)	{
        tc358743_log_status(sd);
    }
}
static void tc358743_set_pll(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct tc358743_platform_data *pdata = &state->pdata;
	u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
	u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
	u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
		SET_PLL_FBD(pdata->pll_fbd);
	u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;

	v4l2_info(sd, "%s:\n", __func__);

	/* Only rewrite when needed (new value or disabled), since rewriting
	 * triggers another format change event. */
	if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
		u16 pll_frs;

		if (hsck > 500000000)
			pll_frs = 0x0;
		else if (hsck > 250000000)
			pll_frs = 0x1;
		else if (hsck > 125000000)
			pll_frs = 0x2;
		else
			pll_frs = 0x3;
		v4l2_info(sd, "%s: updating PLL clock\n", __func__);
		tc358743_sleep_mode(sd, true);
		i2c_wr16(sd, PLLCTL0, pllctl0_new);
		i2c_wr16_and_or(sd, PLLCTL1,
				~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
				(SET_PLL_FRS(pll_frs) | MASK_RESETB |
				 MASK_PLL_EN));
		udelay(10); /* REF_02, Sheet "Source HDMI" */
		i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
		tc358743_sleep_mode(sd, false);
	}
}

static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct tc358743_platform_data *pdata = &state->pdata;
	u32 sys_freq;
	u32 lockdet_ref;
	u32 cec_freq;
	u16 fh_min;
	u16 fh_max;

	sys_freq = pdata->refclk_hz / 10000;
	i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
	i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);

	i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
			(pdata->refclk_hz == 42000000) ? MASK_PHY_SYSCLK_IND : 0x0);

	fh_min = pdata->refclk_hz / 100000;
	i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
	i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);

	fh_max = (fh_min * 66) / 10;
	i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
	i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);

	lockdet_ref = pdata->refclk_hz / 100;
	i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
	i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
	i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);

	i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
			(pdata->refclk_hz == 27000000) ? MASK_NCO_F0_MOD_27MHZ : 0x0);

	/*
	 * Trial and error suggests that the default register value
	 * of 656 is for a 42 MHz reference clock. Use that to derive
	 * a new value based on the actual reference clock.
	 */
	cec_freq = (656 * sys_freq) / 4200;
	i2c_wr16(sd, CECHCLK, cec_freq);
	i2c_wr16(sd, CECLCLK, cec_freq);
}

static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	switch (state->mbus_fmt_code) {
		case MEDIA_BUS_FMT_UYVY8_1X16:
			v4l2_info(sd, "%s: YCbCr 422 16-bit\n", __func__);
			i2c_wr8_and_or(sd, VOUT_SET2,
					~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
					MASK_SEL422 | MASK_VOUT_422FIL_100);
			i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
					MASK_VOUT_COLOR_601_YCBCR_LIMITED);
			mutex_lock(&state->confctl_mutex);
			i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
					MASK_YCBCRFMT_422_8_BIT);
			mutex_unlock(&state->confctl_mutex);
			break;
		//case MEDIA_BUS_FMT_RGB888_1X24:
		//	v4l2_info(sd, "%s: RGB 888 24-bit\n", __func__);
		//	i2c_wr8_and_or(sd, VOUT_SET2,
		//			~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
		//			0x00);
		//	i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
		//			MASK_VOUT_COLOR_RGB_FULL);
		//	mutex_lock(&state->confctl_mutex);
		//	i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
		//	mutex_unlock(&state->confctl_mutex);
		//	break;
		default:
			v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
				__func__, state->mbus_fmt_code);
			break;
	}

	// enable_stream(sd, true);  // Just put here for testing
}

static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct v4l2_bt_timings *bt = &state->timings.bt;
	struct tc358743_platform_data *pdata = &state->pdata;
	u32 bits_pr_pixel =
		(state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ?  16 : 24;
	u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
	u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;

	return DIV_ROUND_UP(bps, bps_pr_lane);
}

static void tc358743_set_csi(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct tc358743_platform_data *pdata = &state->pdata;
	unsigned lanes = tc358743_num_csi_lanes_needed(sd);

	v4l2_info(sd, "%s:\n", __func__);

	state->csi_lanes_in_use = lanes;

	tc358743_reset(sd, MASK_CTXRST);

	if (lanes < 1)
		i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
	if (lanes < 1)
		i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
	if (lanes < 2)
		i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
	if (lanes < 3)
		i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
	if (lanes < 4)
		i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);

	i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
	i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
	i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
	i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
	i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
	i2c_wr32(sd, TWAKEUP, pdata->twakeup);
	i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
	i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
	i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);

	i2c_wr32(sd, HSTXVREGEN,
			((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
			((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
			((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
			((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
			((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));

	i2c_wr32(sd, TXOPTIONCNTRL, (pdata->endpoint.bus.mipi_csi2.flags &
		 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
	i2c_wr32(sd, STARTCNTRL, MASK_START);
	i2c_wr32(sd, CSI_START, MASK_STRT);

	i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
			MASK_ADDRESS_CSI_CONTROL |
			MASK_CSI_MODE |
			MASK_TXHSMD |
			((lanes == 4) ? MASK_NOL_4 :
			 (lanes == 3) ? MASK_NOL_3 :
			 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));

	i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
			MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
			MASK_WCER | MASK_INER);

	i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
			MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);

	i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
			MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
}

static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct tc358743_platform_data *pdata = &state->pdata;

	/* Default settings from REF_02, sheet "Source HDMI"
	 * and custom settings as platform data */
	// turn of physics
	i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
	i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
			SET_FREQ_RANGE_MODE_CYCLES(1));
	i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
			(pdata->hdmi_phy_auto_reset_tmds_detected ?
			 MASK_PHY_AUTO_RST2 : 0) |
			(pdata->hdmi_phy_auto_reset_tmds_in_range ?
			 MASK_PHY_AUTO_RST3 : 0) |
			(pdata->hdmi_phy_auto_reset_tmds_valid ?
			 MASK_PHY_AUTO_RST4 : 0));
	i2c_wr8(sd, PHY_BIAS, 0x40);
	i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
	i2c_wr8(sd, AVM_CTL, 45);
	i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
			pdata->hdmi_detection_delay << 4);

	i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
			(pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
			 MASK_H_PI_RST : 0) |
			(pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
			 MASK_V_PI_RST : 0));
	// turn on physics
	i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
}

static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);

	/* Default settings from REF_02, sheet "Source HDMI" */
	i2c_wr8(sd, FORCE_MUTE, 0x00);
	i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
			MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
			MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
	i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
	i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
	i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
	i2c_wr8(sd, FS_MUTE, 0x00);
	i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
	i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
	i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
	i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
	i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
	i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));

	mutex_lock(&state->confctl_mutex);
	i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
			MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
	mutex_unlock(&state->confctl_mutex);
}

static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
{
	/* Default settings from REF_02, sheet "Source HDMI" */
	i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
			MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
			MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
			MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
	i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
	i2c_wr8(sd, NO_PKT_CLR, 0x53);
	i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
	i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
	i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
}

static void tc358743_initial_setup(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct tc358743_platform_data *pdata = &state->pdata;

	/*
	 * IR is not supported by this driver.
	 * CEC is only enabled if needed.
	 */
	i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
				     (MASK_IRRST | MASK_CECRST));

	tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
#ifdef CONFIG_VIDEO_TC358743_CEC
	tc358743_reset(sd, MASK_CECRST);
#endif
	tc358743_sleep_mode(sd, false);

	i2c_wr16(sd, FIFOCTL, pdata->fifo_level);

	tc358743_set_ref_clk(sd);

	i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
	               pdata->ddc5v_delay & MASK_DDC5V_MODE);

	i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);

	tc358743_set_hdmi_phy(sd);
	tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
	tc358743_set_hdmi_audio(sd);
	tc358743_set_hdmi_info_frame_mode(sd);

	/* All CE and IT formats are detected as RGB full range in DVI mode */
	i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);

	i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
			MASK_VOUTCOLORMODE_AUTO);
	i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
}

/* --------------- CEC --------------- */

#ifdef CONFIG_VIDEO_TC358743_CEC
static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
{
	struct tc358743_state *state = adap->priv;
	struct v4l2_subdev *sd = &state->sd;

	i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
	i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
	i2c_wr32(sd, CECEN, enable);
	if (enable)
		i2c_wr32(sd, CECREN, MASK_CECREN);
	return 0;
}

static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
						bool enable)
{
	struct tc358743_state *state = adap->priv;
	struct v4l2_subdev *sd = &state->sd;
	u32 reg;

	reg = i2c_rd32(sd, CECRCTL1);
	if (enable)
		reg |= MASK_CECOTH;
	else
		reg &= ~MASK_CECOTH;
	i2c_wr32(sd, CECRCTL1, reg);
	return 0;
}

static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
{
	struct tc358743_state *state = adap->priv;
	struct v4l2_subdev *sd = &state->sd;
	unsigned int la = 0;

	if (log_addr != CEC_LOG_ADDR_INVALID) {
		la = i2c_rd32(sd, CECADD);
		la |= 1 << log_addr;
	}
	i2c_wr32(sd, CECADD, la);
	return 0;
}

static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
				   u32 signal_free_time, struct cec_msg *msg)
{
	struct tc358743_state *state = adap->priv;
	struct v4l2_subdev *sd = &state->sd;
	unsigned int i;

	i2c_wr32(sd, CECTCTL,
		 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
		 (signal_free_time - 1));
	for (i = 0; i < msg->len; i++)
		i2c_wr32(sd, CECTBUF1 + i * 4,
			msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
	i2c_wr32(sd, CECTEN, MASK_CECTEN);
	return 0;
}

static const struct cec_adap_ops tc358743_cec_adap_ops = {
	.adap_enable = tc358743_cec_adap_enable,
	.adap_log_addr = tc358743_cec_adap_log_addr,
	.adap_transmit = tc358743_cec_adap_transmit,
	.adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
};

static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus,
				 bool *handled)
{
	struct tc358743_state *state = to_state(sd);
	unsigned int cec_rxint, cec_txint;
	unsigned int clr = 0;

	cec_rxint = i2c_rd32(sd, CECRSTAT);
	cec_txint = i2c_rd32(sd, CECTSTAT);

	if (intstatus & MASK_CEC_RINT)
		clr |= MASK_CECRICLR;
	if (intstatus & MASK_CEC_TINT)
		clr |= MASK_CECTICLR;
	i2c_wr32(sd, CECICLR, clr);

	if ((intstatus & MASK_CEC_TINT) && cec_txint) {
		if (cec_txint & MASK_CECTIEND)
			cec_transmit_attempt_done(state->cec_adap,
						  CEC_TX_STATUS_OK);
		else if (cec_txint & MASK_CECTIAL)
			cec_transmit_attempt_done(state->cec_adap,
						  CEC_TX_STATUS_ARB_LOST);
		else if (cec_txint & MASK_CECTIACK)
			cec_transmit_attempt_done(state->cec_adap,
						  CEC_TX_STATUS_NACK);
		else if (cec_txint & MASK_CECTIUR) {
			/*
			 * Not sure when this bit is set. Treat
			 * it as an error for now.
			 */
			cec_transmit_attempt_done(state->cec_adap,
						  CEC_TX_STATUS_ERROR);
		}
		if (handled)
			*handled = true;
	}
	if ((intstatus & MASK_CEC_RINT) &&
	    (cec_rxint & MASK_CECRIEND)) {
		struct cec_msg msg = {};
		unsigned int i;
		unsigned int v;

		v = i2c_rd32(sd, CECRCTR);
		msg.len = v & 0x1f;
		for (i = 0; i < msg.len; i++) {
			v = i2c_rd32(sd, CECRBUF1 + i * 4);
			msg.msg[i] = v & 0xff;
		}
		cec_received_msg(state->cec_adap, &msg);
		if (handled)
			*handled = true;
	}
	i2c_wr16(sd, INTSTATUS,
		 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
}

#endif

/* --------------- IRQ --------------- */

static void tc358743_format_change(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct v4l2_dv_timings timings;
	const struct v4l2_event tc358743_ev_fmt = {
		.type = V4L2_EVENT_SOURCE_CHANGE,
		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
	};

	v4l2_info(sd, "%s: Format changed\n", __func__);

	if (tc358743_get_detected_timings(sd, &timings)) {
		enable_stream(sd, false);

		v4l2_info(sd, "%s: Format changed. No signal\n", __func__);
	} else {
		if (!tegra_v4l2_match_dv_timings(&state->timings, &timings, 0, false))
			enable_stream(sd, false);

		v4l2_print_dv_timings(sd->name,
				"tc358743_format_change: Format change`d. New format: ",	&timings, false);
	}

	if (sd->devnode)
		v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
}

static void tc358743_init_interrupts(struct v4l2_subdev *sd)
{
	u16 i;

	/* clear interrupt status registers */
	for (i = SYS_INT; i <= KEY_INT; i++)
		i2c_wr8(sd, i, 0xff);

	i2c_wr16(sd, INTSTATUS, 0xffff);
}

static void tc358743_enable_interrupts(struct v4l2_subdev *sd, bool cable_connected)
{
	v4l2_info(sd, "%s: cable connected = %d\n", __func__, cable_connected);

	if (cable_connected) {
		i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
					MASK_M_HDMI_DET) & 0xff);
		i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
		i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
					MASK_M_AF_UNLOCK) & 0xff);
		i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
		i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
	} else {
		i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
		i2c_wr8(sd, CLK_INTM, 0xff);
		i2c_wr8(sd, CBIT_INTM, 0xff);
		i2c_wr8(sd, AUDIO_INTM, 0xff);
		i2c_wr8(sd, MISC_INTM, 0xff);
	}
}

static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,	bool *handled)
{
	u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
	u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;

	i2c_wr8(sd, AUDIO_INT, audio_int);

	v4l2_info(sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);

	tc358743_s_ctrl_audio_sampling_rate(sd);
	tc358743_s_ctrl_audio_present(sd);
}

static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
{
	v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));

	i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
}

static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, bool *handled)
{
	u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
	u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;

	i2c_wr8(sd, MISC_INT, misc_int);

	v4l2_info(sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);

	if (misc_int & MASK_I_SYNC_CHG) {
		/* Reset the HDMI PHY to try to trigger proper lock on the
		 * incoming video format. Erase BKSV to prevent that old keys
		 * are used when a new source is connected. */
		if (no_sync(sd) || no_signal(sd)) {
			tc358743_reset_phy(sd);
			tc358743_erase_bksv(sd);
		}

		tc358743_format_change(sd);

		misc_int &= ~MASK_I_SYNC_CHG;
		if (handled)
			*handled = true;
	}

	if (misc_int) {
		v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",	__func__, misc_int);
	}
}

static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, bool *handled)
{
	u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
	u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;

	i2c_wr8(sd, CBIT_INT, cbit_int);

	v4l2_info(sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);

	if (cbit_int & MASK_I_CBIT_FS) {

		v4l2_info(sd, "%s: Audio sample rate changed\n", __func__);
		tc358743_s_ctrl_audio_sampling_rate(sd);

		cbit_int &= ~MASK_I_CBIT_FS;
		if (handled)
			*handled = true;
	}

	if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {

		v4l2_info(sd, "%s: Audio present changed\n", __func__);
		tc358743_s_ctrl_audio_present(sd);

		cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
		if (handled)
			*handled = true;
	}

	if (cbit_int) {
		v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", __func__, cbit_int);
	}
}

static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
{
	u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
	u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;

	/* Bit 7 and bit 6 are set even when they are masked */
	i2c_wr8(sd, CLK_INT, clk_int |0x80 | MASK_I_OUT_H_CHG);

	v4l2_info(sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);

	if (clk_int & (MASK_I_IN_DE_CHG)) {

		v4l2_info(sd, "%s: DE size or position has changed\n",
				__func__);

		/* If the source switch to a new resolution with the same pixel
		 * frequency as the existing (e.g. 1080p25 -> 720p50), the
		 * I_SYNC_CHG interrupt is not always triggered, while the
		 * I_IN_DE_CHG interrupt seems to work fine. Format change
		 * notifications are only sent when the signal is stable to
		 * reduce the number of notifications. */
		if (!no_signal(sd) && !no_sync(sd))
			tc358743_format_change(sd);

		clk_int &= ~(MASK_I_IN_DE_CHG);
		if (handled)
			*handled = true;
	}

	if (clk_int) {
		v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", __func__, clk_int);
	}
}

static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
{
	struct tc358743_state *state = to_state(sd);
	u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
	u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;

	i2c_wr8(sd, SYS_INT, sys_int);

	v4l2_info(sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);

	if (sys_int & MASK_I_DDC) {
		bool tx_5v = tx_5v_power_present(sd);

		v4l2_info(sd, "%s: Tx 5V power present: %s\n",	__func__, tx_5v ?  "yes" : "no");

		if (tx_5v) {
			tc358743_enable_edid(sd);
		} else {
			tc358743_enable_interrupts(sd, false);
			tc358743_disable_edid(sd);
			memset(&state->timings, 0, sizeof(state->timings));
			tc358743_erase_bksv(sd);
			tc358743_update_controls(sd);
		}

		sys_int &= ~MASK_I_DDC;
		if (handled)
			*handled = true;
	}

	if (sys_int & MASK_I_DVI) {
		v4l2_info(sd, "%s: HDMI->DVI change detected\n", __func__);

		/* Reset the HDMI PHY to try to trigger proper lock on the
		 * incoming video format. Erase BKSV to prevent that old keys
		 * are used when a new source is connected. */
		if (no_sync(sd) || no_signal(sd)) {
			tc358743_reset_phy(sd);
			tc358743_erase_bksv(sd);
		}

		sys_int &= ~MASK_I_DVI;
		if (handled)
			*handled = true;
	}

	if (sys_int & MASK_I_HDMI) {
		v4l2_info(sd, "%s: DVI->HDMI change detected\n", __func__);

		/* Register is reset in DVI mode (REF_01, c. 6.6.41) */
		i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);

		sys_int &= ~MASK_I_HDMI;
		if (handled)
			*handled = true;
	}

	if (sys_int) {
		v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", __func__, sys_int);
	}
}

/* --------------- CORE OPS --------------- */

static int tc358743_log_status(struct v4l2_subdev *sd)
{
	struct tc358743_state *state = to_state(sd);
	struct v4l2_dv_timings timings;
	uint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
	uint16_t sysctl = i2c_rd16(sd, SYSCTL);
	u8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);
	const int deep_color_mode[4] = { 8, 10, 12, 16 };
	static const char * const input_color_space[] = {
		"RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)",
		"xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
		"NA(10)", "NA(11)", "NA(12)", "opYCC 601"};
	tc358743_get_edid(sd);
	v4l2_info(sd, "=====BEGIN TC358743 LOG=====");
	v4l2_info(sd, "-----Chip status-----\n");
	v4l2_info(sd, "Chip ID: 0x%02x\n",
			(i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
	v4l2_info(sd, "Chip revision: 0x%02x\n",
			i2c_rd16(sd, CHIPID) & MASK_REVID);
	v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
			!!(sysctl & MASK_IRRST),
			!!(sysctl & MASK_CECRST),
			!!(sysctl & MASK_CTXRST),
			!!(sysctl & MASK_HDMIRST));
	v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
	v4l2_info(sd, "Cable detected (+5V power): %s\n",
			hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
	v4l2_info(sd, "DDC lines enabled: %s\n",
			(i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
			"yes" : "no");
	v4l2_info(sd, "Hotplug enabled: %s\n",
			(i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
			"yes" : "no");
	v4l2_info(sd, "CEC enabled: %s\n",
			(i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
	v4l2_info(sd, "-----Signal status-----\n");
	v4l2_info(sd, "TMDS signal detected: %s\n",
			hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
	v4l2_info(sd, "Stable sync signal: %s\n",
			hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
	v4l2_info(sd, "PHY PLL locked: %s\n",
			hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
	v4l2_info(sd, "PHY DE detected: %s\n",
			hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");

	if (tc358743_get_detected_timings(sd, &timings)) {
		v4l2_info(sd, "No video detected\n");
	} else {
		v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, true);
	}
	v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, true);

	v4l2_info(sd, "-----CSI-TX status-----\n");
	v4l2_info(sd, "Lanes needed: %d\n",
			tc358743_num_csi_lanes_needed(sd));
	v4l2_info(sd, "Lanes in use: %d\n",
			state->csi_lanes_in_use);
	v4l2_info(sd, "Waiting for particular sync signal: %s\n",
			(i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
			"yes" : "no");
	v4l2_info(sd, "Transmit mode: %s\n",
			(i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
			"yes" : "no");
	v4l2_info(sd, "Receive mode: %s\n",
			(i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
			"yes" : "no");
	v4l2_info(sd, "Stopped: %s\n",
			(i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
			"yes" : "no");
	v4l2_info(sd, "Color space: %s\n",
			state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
			"YCbCr 422 16-bit" :
			state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
			"RGB 888 24-bit" : "Unsupported");

	v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
	v4l2_info(sd, "HDCP encrypted content: %s\n",
			hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
	v4l2_info(sd, "Input color space: %s %s range\n",
			input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
			(vi_status3 & MASK_LIMITED) ? "limited" : "full");
	if (is_hdmi(sd)) {
		v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
				"off");
		v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
				deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
					MASK_S_DEEPCOLOR) >> 2]);
		print_avi_infoframe(sd);
	}
	v4l2_info(sd, "=====END TC358743 LOG=====");

	return 0;
}

#ifdef CONFIG_VIDEO_ADV_DEBUG
static void tc358743_print_register_map(struct v4l2_subdev *sd)
{
	v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
	v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
	v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
	v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
	v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
	v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
	v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
	v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
	v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
	v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
	v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
	v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
	v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
	v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
	v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
	v4l2_info(sd, "0x9300-      : Reserved\n");
}

static int tc358743_get_reg_size(u16 address)
{
	/* REF_01 p. 66-72 */
	if (address <= 0x00ff)
		return 2;
	else if ((address >= 0x0100) && (address <= 0x06FF))
		return 4;
	else if ((address >= 0x0700) && (address <= 0x84ff))
		return 2;
	else
		return 1;
}

static int tc358743_g_register(struct v4l2_subdev *sd,
			                   struct v4l2_dbg_register *reg)
{
	if (reg->reg > 0xffff) {
		tc358743_print_register_map(sd);
		return -EINVAL;
	}

	reg->size = tc358743_get_reg_size(reg->reg);

	reg->val = i2c_rdreg(sd, reg->reg, reg->size);

	return 0;
}

static int tc358743_s_register(struct v4l2_subdev *sd,
			             const struct v4l2_dbg_register *reg)
{
	if (reg->reg > 0xffff) {
		tc358743_print_register_map(sd);
		return -EINVAL;
	}

	/* It should not be possible for the user to enable HDCP with a simple
	 * v4l2-dbg command.
	 *
	 * DO NOT REMOVE THIS unless all other issues with HDCP have been
	 * resolved.
	 */
	if (reg->reg == HDCP_MODE ||
	    reg->reg == HDCP_REG1 ||
	    reg->reg == HDCP_REG2 ||
	    reg->reg == HDCP_REG3 ||
	    reg->reg == BCAPS)
		return 0;

	i2c_wrreg(sd, (u16)reg->reg, reg->val,
			tc358743_get_reg_size(reg->reg));

	return 0;
}
#endif

static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
{
	u16 intstatus = i2c_rd16(sd, INTSTATUS);

	v4l2_info(sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);

	if (intstatus & MASK_HDMI_INT) {
		u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
		u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);

		if (hdmi_int0 & MASK_I_MISC)
			tc358743_hdmi_misc_int_handler(sd, handled);
		if (hdmi_int1 & MASK_I_CBIT)
			tc358743_hdmi_cbit_int_handler(sd, handled);
		if (hdmi_int1 & MASK_I_CLK)
			tc358743_hdmi_clk_int_handler(sd, handled);
		if (hdmi_int1 & MASK_I_SYS)
			tc358743_hdmi_sys_int_handler(sd, handled);
		if (hdmi_int1 & MASK_I_AUD)
			tc358743_hdmi_audio_int_handler(sd, handled);

		i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
		intstatus &= ~MASK_HDMI_INT;
	}

#ifdef CONFIG_VIDEO_TC358743_CEC
	if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
		tc358743_cec_handler(sd, intstatus, handled);
		i2c_wr16(sd, INTSTATUS,
			 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
		intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
	}
#endif

	if (intstatus & MASK_CSI_INT) {
		u32 csi_int = i2c_rd32(sd, CSI_INT);

		if (csi_int & MASK_INTER)
			tc358743_csi_err_int_handler(sd, handled);

		i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
	}

	intstatus = i2c_rd16(sd, INTSTATUS);
	if (intstatus) {
		v4l2_info(sd,
				"%s: Unhandled IntStatus interrupts: 0x%02x\n",
				__func__, intstatus);
	}

	return 0;
}

static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
{
	struct tc358743_state *state = dev_id;
	bool handled = false;

	tc358743_isr(&state->sd, 0, &handled);

	return handled ? IRQ_HANDLED : IRQ_NONE;
}

static void tc358743_irq_poll_timer(struct timer_list *t)
{
	struct tc358743_state *state = from_timer(state, t, timer);
	unsigned int msecs;

	schedule_work(&state->work_i2c_poll);
	/*
	 * If CEC is present, then we need to poll more frequently,
	 * otherwise we will miss CEC messages.
	 */
	msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
	mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
}

static void tc358743_work_i2c_poll(struct work_struct *work)
{
	struct tc358743_state *state = container_of(work,
			struct tc358743_state, work_i2c_poll);
	bool handled;

	tc358743_isr(&state->sd, 0, &handled);
}

static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
				    struct v4l2_event_subscription *sub)
{
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);
	switch (sub->type) {
	case V4L2_EVENT_SOURCE_CHANGE:
		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
	case V4L2_EVENT_CTRL:
		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
	default:
		return -EINVAL;
	}
}

/* --------------- VIDEO OPS --------------- */

static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
				 struct v4l2_dv_timings *timings)
{
	struct tc358743_state *state = to_state(sd);
	v4l2_info(sd, "%s\n",__func__);
	if (!timings)
		return -EINVAL;

	if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
		v4l2_info(sd, "%s: no change\n", __func__);
		return 0;
	}

	if (!v4l2_valid_dv_timings(timings,	&tc358743_timings_cap, NULL, NULL)) {
		v4l2_err(sd, "%s: timings out of range\n", __func__);
		return -ERANGE;
	}

	state->timings = *timings;

	enable_stream(sd, false);
	tc358743_set_pll(sd);
	tc358743_set_csi(sd);

	return 0;
}

static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
				 struct v4l2_dv_timings *timings)
{
	struct tc358743_state *state = to_state(sd);
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);

	*timings = state->timings;

	return 0;
}

static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
				    struct v4l2_enum_dv_timings *timings)
{
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);
	if (timings->pad != 0) {
		v4l2_err(sd, "%s: failed %d\n", __func__, EINVAL);
		return -EINVAL;
	}

	return v4l2_enum_dv_timings_cap(timings, &tc358743_timings_cap, NULL, NULL);
}

static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
		struct v4l2_dv_timings *timings)
{
	int ret;
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);

	ret = tc358743_get_detected_timings(sd, timings);
	if (ret) {
		v4l2_err(sd, "%s: @@@@@ timings detected error\n", __func__);
		return ret;
	}

	if (debug)
		v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
				timings, false);

	if (!v4l2_valid_dv_timings(timings,
				&tc358743_timings_cap, NULL, NULL)) {
		v4l2_err(sd, "%s: @@@@@ timings out of range\n", __func__);
		return -ERANGE;
	}

	return 0;
}

static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
		struct v4l2_dv_timings_cap *cap)
{
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);
	if (cap->pad != 0)
		return -EINVAL;

	*cap = tc358743_timings_cap;

	return 0;
}

static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	struct tc358743_state *state = to_state(sd);
	struct v4l2_dv_timings *timings = &(state->timings);

	v4l2_info(sd, "Calling %s\n", __FUNCTION__);
	*status = 0;
	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
	*status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;

	v4l2_info(sd, "%s: status = 0x%x\n", __func__, *status);

	v4l2_info(sd, "Now getting and setting dv timings");
	tc358743_query_dv_timings(sd, timings);
	tc358743_s_dv_timings(sd, timings);

	return 0;
}

static int tc358743_get_mbus_config(struct v4l2_subdev *sd,
				    unsigned int pad,
				    struct v4l2_mbus_config *cfg)
{
	struct tc358743_state *state = to_state(sd);

	cfg->type = V4L2_MBUS_CSI2_DPHY;

	/* Support for non-continuous CSI-2 clock is missing in the driver */
	cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;

	switch (state->csi_lanes_in_use) {
	case 1:
		cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
		break;
	case 2:
		cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
		break;
	case 3:
		cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
		break;
	case 4:
		cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
{
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);
	v4l2_err(sd, "Calling %s\n", __FUNCTION__);
	/* FIXME: show log status for test */
	/*hainh
	enable_stream(sd, enable);
	if (enable)
		tc358743_log_status(sd);
	*/
	enable_stream(sd, true);
	// if (true)
	// 	tc358743_log_status(sd);

	if (!enable) {
		/* Put all lanes in LP-11 state (STOPSTATE) */
		tc358743_set_csi(sd);
	}

	return 0;
}

/* --------------- PAD OPS --------------- */

static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
		struct v4l2_subdev_pad_config *cfg,
		struct v4l2_subdev_mbus_code_enum *code)
{
	v4l2_info(sd, "%s()\n", __func__);

//	if (code->index >= 2) {
//		v4l2_err(sd, "Error in %s\n", __FUNCTION__);
//		return -EINVAL;
//	}

	switch (code->index) {
	case 0:
		code->code = MEDIA_BUS_FMT_RGB888_1X24;
		break;
	case 1:
		code->code = MEDIA_BUS_FMT_UYVY8_1X16;
		break;
	default:
		return -EINVAL;
	}

	v4l2_info(sd, "Mbus code found succsefully (%d: %d)", code->index, code->code);

	return 0;
}

static int tc358743_get_fmt(struct v4l2_subdev *sd,
		struct v4l2_subdev_pad_config *cfg,
		struct v4l2_subdev_format *format)
{
	struct tc358743_state *state = to_state(sd);
	u8 vi_rep = i2c_rd8(sd, VI_REP);
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);

	if (format->pad != 0) {
		v4l2_err(sd, "%s Error\n", __FUNCTION__);
		return -EINVAL;
	}

	format->format.code = state->mbus_fmt_code;
	format->format.width = state->timings.bt.width;
	format->format.height = state->timings.bt.height;
	format->format.field = V4L2_FIELD_NONE;


	switch (vi_rep & MASK_VOUT_COLOR_SEL) {
	case MASK_VOUT_COLOR_RGB_FULL:
	case MASK_VOUT_COLOR_RGB_LIMITED:
		format->format.colorspace = V4L2_COLORSPACE_SRGB;
		break;
	case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
	case MASK_VOUT_COLOR_601_YCBCR_FULL:
		v4l2_info(sd, "Here 6b, colorspace: %d\n", V4L2_COLORSPACE_SMPTE170M);
		format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
		break;
	case MASK_VOUT_COLOR_709_YCBCR_FULL:
	case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
		format->format.colorspace = V4L2_COLORSPACE_REC709;
		break;
	default:
		format->format.colorspace = 0;
        v4l2_info(sd,"%d:%s colorspace = 0\n",__LINE__,__FUNCTION__);
		break;
	}

	v4l2_info(sd, "get fmt complete\n");
	v4l2_info(sd, "format width %d\n", format->format.width);
	v4l2_info(sd, "format height %d\n", format->format.height);

	v4l2_info(sd, "fmt_code: %d\n", format->format.code);
	v4l2_info(sd, "RGB888 code: %d\n", MEDIA_BUS_FMT_RGB888_1X24);
	v4l2_info(sd, "UYVY8 code: %d\n", MEDIA_BUS_FMT_UYVY8_1X16);
	return 0;
}


static int tc358743_set_fmt(struct v4l2_subdev *sd,
		struct v4l2_subdev_pad_config *cfg,
		struct v4l2_subdev_format *format)
{
	struct tc358743_state *state = to_state(sd);
	u32 code = format->format.code;
	int ret = tc358743_get_fmt(sd, cfg, format);

	v4l2_dbg(3, debug, sd, "%s(), ret: %d\n", __func__, ret);
	v4l2_dbg(3, debug, sd, "Set format code: %d\n", code);

	format->format.code = code;

	if (ret)
		return ret;

	switch (code) {
		case MEDIA_BUS_FMT_RGB888_1X24:
		case MEDIA_BUS_FMT_UYVY8_1X16:
			v4l2_dbg(3, debug, sd, "Good code %d\n", code);
			break;
		default:
			v4l2_err(sd, "Bad code %d\n", code);
			return -EINVAL;
	}

	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
		return 0;

	state->mbus_fmt_code = format->format.code;

	enable_stream(sd, false);
	tc358743_set_pll(sd);
	tc358743_set_csi(sd);
	tc358743_set_csi_color_space(sd);
	v4l2_info(sd, "Called %s, completed successfully\n", __FUNCTION__);
	return 0;
}

static int tc358743_g_edid(struct v4l2_subdev *sd,
		struct v4l2_subdev_edid *edid)
{
	struct tc358743_state *state = to_state(sd);
	// int i= 0;
	v4l2_info(sd, "Calling %s\n", __FUNCTION__);

	if (edid->pad != 0)
		return -EINVAL;

	if (edid->start_block == 0 && edid->blocks == 0) {
		edid->blocks = state->edid_blocks_written;
		return 0;
	}

	if (state->edid_blocks_written == 0)
		return -ENODATA;

	if (edid->start_block >= state->edid_blocks_written || edid->blocks == 0)
		return -EINVAL;

	if (edid->start_block + edid->blocks > state->edid_blocks_written)
		edid->blocks = state->edid_blocks_written - edid->start_block;

	i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
			edid->blocks * EDID_BLOCK_SIZE);
	v4l2_info(sd,"EDID_RAM has %d byte from: 0x%04x to 0x%04x \r\n",
		edid->blocks * EDID_BLOCK_SIZE,
		EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE),
		EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE) +
		edid->blocks * EDID_BLOCK_SIZE);
	// for(i= 0;i<edid->blocks * EDID_BLOCK_SIZE;i++){
	// 	printk("%02x ",edid->edid[i]);
	// }
	// v4l2_info(sd,"\r\n");
	v4l2_info(sd, "%s completed successfully", __FUNCTION__);
	return 0;
}

static int tc358743_s_edid(struct v4l2_subdev *sd,
				struct v4l2_subdev_edid *edid)
{
	struct tc358743_state *state = to_state(sd);
	u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
	u16 pa;
	int err;
	int i;

	v4l2_info(sd, "%s, pad %d, start block %d, blocks %d\n",
		 __func__, edid->pad, edid->start_block, edid->blocks);

	if (edid->pad != 0)
		return -EINVAL;

	if (edid->start_block != 0)
		return -EINVAL;

	if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
		edid->blocks = EDID_NUM_BLOCKS_MAX;
		return -E2BIG;
	}

	pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
	err = v4l2_phys_addr_validate(pa, &pa, NULL);
	if (err)
		return err;

	cec_phys_addr_invalidate(state->cec_adap);

	tc358743_disable_edid(sd);

	i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
	i2c_wr8(sd, EDID_LEN2, edid_len >> 8);

	if (edid->blocks == 0) {
		state->edid_blocks_written = 0;
		return 0;
	}
	#if 0
	i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
	#else
	for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
		i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
	#endif
	state->edid_blocks_written = edid->blocks;

	cec_s_phys_addr(state->cec_adap, pa, false);

//	if (tx_5v_power_present(sd))
		tc358743_enable_edid(sd);

	v4l2_info(sd, "%s completed successfully", __FUNCTION__);
	return 0;
}
// static int tc358743_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
// {
// 	struct tc358743_state *state = to_state(sd);
// 	u8 vi_rep = i2c_rd8(sd, VI_REP);

// 	mf->code = state->mbus_fmt_code;
// 	mf->width = state->timings.bt.width;
// 	mf->height = state->timings.bt.height;
// 	mf->field = V4L2_FIELD_NONE;
// 	switch (vi_rep & MASK_VOUT_COLOR_SEL) {
// 		case MASK_VOUT_COLOR_RGB_FULL:
// 		case MASK_VOUT_COLOR_RGB_LIMITED:
// 			mf->colorspace = V4L2_COLORSPACE_SRGB;
// 			break;
// 		case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
// 		case MASK_VOUT_COLOR_601_YCBCR_FULL:
// 			mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
// 			break;
// 		case MASK_VOUT_COLOR_709_YCBCR_FULL:
// 		case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
// 			mf->colorspace = V4L2_COLORSPACE_REC709;
// 			break;
// 		default:
// 			mf->colorspace = 0;
// 			break;
// 	}
// 	return 0;
// }

static int tc358743_enum_frame_size(struct v4l2_subdev *sd,
				                    struct v4l2_subdev_pad_config  *cfg,
				                    struct v4l2_subdev_frame_size_enum *fse)
{
	const struct camera_common_frmfmt *frmfmt = tc358743_frmfmt;
	int num_frmfmt = ARRAY_SIZE(tc358743_frmfmt);

	v4l2_info(sd, "%s()\n", __func__);
	v4l2_info(sd, "fse->code %d, index %d\n", fse->code, fse->index);
	v4l2_info(sd, "----------------------------------------\n");

	// fse->min_width  = fse->max_width  = 1280;
	// fse->min_height = fse->max_height = 720;

	v4l2_info(sd, "Trying to find frmfmt that matches fse->code, code: %d (UYVY: %d, ARGB32: %d, MEDIA_BUS_FMT_UYVY8_1X16: %d, MEDIA_BUS_FMT_RGB888_1X24: %d)\n", fse->code, V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_RGB888_1X24);

	if (fse->code != MEDIA_BUS_FMT_UYVY8_1X16 && fse->code != V4L2_PIX_FMT_ABGR32 && fse->code != MEDIA_BUS_FMT_UYVY8_1X16) {
		v4l2_err(sd, "Error in %s fse->code, code: %d, UYVY: %d, ARGB32: %d\n", __FUNCTION__, fse->code, V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_ABGR32);
		return -EINVAL;
	}

	v4l2_info(sd, "Code ok");

	if (fse->index >= num_frmfmt) {
		v4l2_err(sd, "Error in %s, %d outside of num_frmfmt (%d)", __FUNCTION__, fse->index, num_frmfmt);
		return -EINVAL;
	}

	v4l2_info(sd, "Index ok");

	fse->min_width  = fse->max_width  = frmfmt[fse->index].size.width;
	fse->min_height = fse->max_height = frmfmt[fse->index].size.height;
	v4l2_info(sd, "!!!!!!!!! %s() complete successfully, width: %d, height: %d\n", __func__, fse->min_width, fse->min_height);
	return 0;
}

static int tc358743_enum_frame_interval(struct v4l2_subdev *sd,
				                        struct v4l2_subdev_pad_config  *cfg,
				                        struct v4l2_subdev_frame_interval_enum *fie)
{
	const struct camera_common_frmfmt *frmfmt = tc358743_frmfmt;
	int num_frmfmt = ARRAY_SIZE(tc358743_frmfmt);
	int i;

	v4l2_info(sd, "%s()\n", __func__);
	v4l2_info(sd, "----------------------------------------\n");

	v4l2_info(sd, "Trying to find frame interfval that matches fie->code, code: %d (UYVY: %d, ARGB32: %d, MEDIA_BUS_FMT_UYVY8_1X16: %d)\n", fie->code, V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_UYVY8_1X16);


	if (fie->code != V4L2_PIX_FMT_UYVY &&
	    fie->code != V4L2_PIX_FMT_ABGR32 && fie->code != MEDIA_BUS_FMT_UYVY8_1X16) {
		v4l2_err(sd, "Unexpected code (%d), UYUV: %d, ABGR32: %d\n", fie->code, V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_ABGR32);
		return -EINVAL;
	}

	v4l2_info(sd, "Code ok");

	for (i = 0; i < num_frmfmt; i++) {
		if (frmfmt[i].size.width == fie->width && frmfmt[i].size.height == fie->height) {
			v4l2_info(sd, "Matched width %d and %d, height %d and %d", frmfmt[i].size.width, fie->width, frmfmt[i].size.height, fie->height);
			break;
		}
	}

	v4l2_info(sd, "w/h ok or end (i=%d, num=%d)", i, num_frmfmt);

	if (i >= num_frmfmt) {
		v4l2_err(sd, "Error in %s, num frmfmt\n", __FUNCTION__);
		return -EINVAL;
	}

	v4l2_info(sd, "i ok");

	if (fie->index >= frmfmt[i].num_framerates) {
		v4l2_err(sd, "Error in %s num framerates (%d outside %d)\n", __FUNCTION__, fie->index, frmfmt[i].num_framerates);
		return -EINVAL;
	}

	v4l2_info(sd, "index ok");

	fie->interval.numerator = 1;
	fie->interval.denominator = frmfmt[i].framerates[fie->index];
	v4l2_info(sd, "!!!!!!!!!! %s() completed successfully, interval: 1/%d\n", __func__, fie->interval.denominator);
	return 0;
}

static int tc358743_s_power(struct v4l2_subdev *sd, int on)
{
	return 0;
}

/* -------------------------------------------------------------------------- */

static const struct v4l2_subdev_core_ops tc358743_core_ops = {
	.s_power = tc358743_s_power,
	.log_status = tc358743_log_status,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = tc358743_g_register,
	.s_register = tc358743_s_register,
#endif
	.interrupt_service_routine = tc358743_isr,
	.subscribe_event = tc358743_subscribe_event,
	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
};

static const struct v4l2_subdev_video_ops tc358743_video_ops = {
	.g_input_status = tc358743_g_input_status,
	.s_dv_timings = tc358743_s_dv_timings,
	.g_dv_timings = tc358743_g_dv_timings,
	.query_dv_timings = tc358743_query_dv_timings,
	.s_stream = tc358743_s_stream,
};

static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
	.enum_mbus_code = tc358743_enum_mbus_code,
	.set_fmt = tc358743_set_fmt,
	.get_fmt = tc358743_get_fmt,
	.get_edid = tc358743_g_edid,
	.set_edid = tc358743_s_edid,
	.enum_dv_timings = tc358743_enum_dv_timings,
	.dv_timings_cap = tc358743_dv_timings_cap,
	.enum_frame_size = tc358743_enum_frame_size,
	.enum_frame_interval = tc358743_enum_frame_interval,
	.get_mbus_config = tc358743_get_mbus_config,
};

static const struct v4l2_subdev_ops tc358743_ops = {
	.core = &tc358743_core_ops,
	.video = &tc358743_video_ops,
	.pad = &tc358743_pad_ops,
};

/* --------------- CUSTOM CTRLS --------------- */

static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
	.id = TC358743_CID_AUDIO_SAMPLING_RATE,
	.name = "Audio sampling rate",
	.type = V4L2_CTRL_TYPE_INTEGER,
	.min = 0,
	.max = 768000,
	.step = 1,
	.def = 0,
	.flags = V4L2_CTRL_FLAG_READ_ONLY,
};

static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
	.id = TC358743_CID_AUDIO_PRESENT,
	.name = "Audio present",
	.type = V4L2_CTRL_TYPE_BOOLEAN,
	.min = 0,
	.max = 1,
	.step = 1,
	.def = 0,
	.flags = V4L2_CTRL_FLAG_READ_ONLY,
};

static bool tc358743_parse_dt(struct tc358743_platform_data *pdata,
		struct i2c_client *client)
{
	struct device_node *node = client->dev.of_node;
	const u32 *property;

	v4l_dbg(1, debug, client, "Device Tree Parameters:\n");

	pdata->reset_gpio = of_get_named_gpio(node, "reset-gpios", 0);
	if (pdata->reset_gpio == 0)
		return false;
	v4l_dbg(1, debug, client, "reset_gpio = %d\n", pdata->reset_gpio);

	property = of_get_property(node, "refclk_hz", NULL);
	if (property == NULL)
		return false;
	pdata->refclk_hz = be32_to_cpup(property);
	v4l_dbg(1, debug, client, "refclk_hz = %d\n", be32_to_cpup(property));

	return true;
}

#ifdef CONFIG_OF
static void tc358743_gpio_reset(struct tc358743_state *state)
{

	usleep_range(5000, 10000);
	// TODO: Re-implement the reset GPIO!
	//~ gpiod_set_value(state->reset_gpio, 1);
    // gpio_set_value((int)state->reset_gpio, 1);
	usleep_range(1000, 2000);
    // gpio_set_value((int)state->reset_gpio, 0);
	//~ gpiod_set_value(state->reset_gpio, 0);
	msleep(20);
}

static int tc358743_probe_of(struct tc358743_state *state)
{
	struct device *dev = &state->i2c_client->dev;
	struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
	struct device_node *ep;
	struct clk *refclk;
	u32 bps_pr_lane;
	int ret;

	// refclk = devm_clk_get(dev, "cam_mclk1");
	// if (IS_ERR(refclk)) {
	// 	if (PTR_ERR(refclk) != -EPROBE_DEFER)
	// 		dev_err(dev, "failed to get refclk: %ld\n",
	// 			PTR_ERR(refclk));
	// 	return PTR_ERR(refclk);
	// }


	refclk = devm_clk_get(dev, "extperiph1");
	if (IS_ERR(refclk)) {
		if (PTR_ERR(refclk) != -EPROBE_DEFER)
			dev_err(dev, "failed to get refclk from extperiph1: %ld\n",
			PTR_ERR(refclk));
	//      return PTR_ERR(refclk);
	}

	ret = clk_prepare_enable(refclk);
	if (ret) {
		dev_err(dev, "Failed! to enable clock\n");
		return ret;
	}

	state->pdata.refclk_hz = clk_get_rate(refclk);
	ret = clk_set_rate(refclk, 27000000);  // this will set it to 27200000
	if (ret < 0) {
		dev_err(dev, "failed to set refclk rate to %d (currently %d)", 27000000, state->pdata.refclk_hz);
		return ret;
	}
	state->pdata.refclk_hz = 27000000; // hardcode to 27000000



	ep = of_graph_get_next_endpoint(dev->of_node, NULL);
	if (!ep) {
		dev_err(dev, "missing endpoint node\n");
		return -EINVAL;
	}

	ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
	if (ret) {
		dev_err(dev, "failed to parse endpoint\n");
		goto put_node;
	}

	if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
	    endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
	    endpoint.nr_of_link_frequencies == 0) {
		dev_err(dev, "missing CSI-2 properties in endpoint\n");
		ret = -EINVAL;
		goto free_endpoint;
	}

	pr_info("tc358743 endpoint.bus.mipi_csi2.flags %d\n",
		endpoint.bus.mipi_csi2.flags);
	pr_info("tc358743 endpoint.bus.mipi_csi2.clock_lane %d\n",
		endpoint.bus.mipi_csi2.clock_lane);
	pr_info("tc358743 endpoint.bus.mipi_csi2.num_data_lanes %d\n",
		endpoint.bus.mipi_csi2.num_data_lanes);
	pr_info("tc358743 endpoint.bus.mipi_csi2.data_lanes [%d-%d-%d-%d]\n",
			endpoint.bus.mipi_csi2.data_lanes[0],
			endpoint.bus.mipi_csi2.data_lanes[1],
			endpoint.bus.mipi_csi2.data_lanes[2],
			endpoint.bus.mipi_csi2.data_lanes[3]);
    pr_info("tc358743 endpoint.nr_of_link_frequencies %d\n",
    	endpoint.nr_of_link_frequencies);

	// state->bus = endpoint.bus.mipi_csi2;
    // pr_info("tc358743 state->bus %s\n",state->bus);
	// clk_prepare_enable(refclk);

	// state->pdata.refclk_hz = clk_get_rate(refclk);
	state->pdata.refclk_hz = 27000000;
    // if ((state->pdata.refclk_hz != 26000000) ||
    //     (state->pdata.refclk_hz != 27000000) ||
    //     (state->pdata.refclk_hz != 42000000))
    // {
    //     pr_info("Set new clock\n");
    //     if (0 != clk_set_rate(refclk,27000000))
    //     {
    //         pr_info("Error: Set new clock\n");
    //     }
    // }

	state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
	state->pdata.hdmi_detection_delay = HDMI_MODE_DELAY_100_MS;
	state->pdata.enable_hdcp = false;
	/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
	state->pdata.fifo_level = 16;
	/*
	 * The PLL input clock is obtained by dividing refclk by pll_prd.
	 * It must be between 6 MHz and 40 MHz, lower frequency is better.
	 */
	switch (state->pdata.refclk_hz) {
    //~ case 26322581:
        //~ state->pdata.refclk_hz = 26322581;
	case 26000000:
	case 27000000:
	//~ case 40800000: /* Tegra */
	case 42000000:
		state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
		break;
	default:
		dev_err(dev, "Unsupported refclk rate: %u Hz\n",
			state->pdata.refclk_hz);
		goto disable_clk;
	}

	/*
	 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
	 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
	 */
	bps_pr_lane = 2 * endpoint.link_frequencies[0];
	//if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
	if (bps_pr_lane < 62500000U || bps_pr_lane > 1188000000U) {
		dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
		ret = -EINVAL;
		goto disable_clk;
	}

	/* The CSI speed per lane is refclk / pll_prd * pll_fbd */
	state->pdata.pll_fbd = bps_pr_lane /
			       state->pdata.refclk_hz * state->pdata.pll_prd;

	/*
	 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
	 * link frequency). In principle it should be possible to calculate
	 * them based on link frequency and resolution.
	 */
	if (bps_pr_lane != 594000000U)
		dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
	pr_info("tc358743 state->pdata.pll_prd=%d\r\n",state->pdata.pll_prd);
	pr_info("tc358743 state->pdata.pll_fbd=%d\r\n",state->pdata.pll_fbd);

	// freq = refclk / prd * fbd, default = 594 MHz
	state->pdata.lineinitcnt = 0xe80;
	state->pdata.lptxtimecnt = 0x003;
	/* tclk-preparecnt: 3, tclk-zerocnt: 20 */
	state->pdata.tclk_headercnt = 0x1403;
	state->pdata.tclk_trailcnt = 0x00;
	/* ths-preparecnt: 3, ths-zerocnt: 1 */
	state->pdata.ths_headercnt = 0x0103;
	state->pdata.twakeup = 0x4882;
	state->pdata.tclk_postcnt = 0x008;
	state->pdata.ths_trailcnt = 0x2;
	state->pdata.hstxvregcnt = 2;
/*richard you*/
	//state->pdata.pll_prd        = 4;
#ifdef TC358743_VOUT_RGB
	state->pdata.pll_fbd        = 132;

	// timing setting
	state->pdata.lineinitcnt    = 0x00000fa0;
	state->pdata.lptxtimecnt    = 0x00000005;
	state->pdata.tclk_headercnt = 0x00001603;
	state->pdata.tclk_trailcnt  = 0x00000001;
	state->pdata.ths_headercnt  = 0x00000603;
	state->pdata.twakeup        = 0x000032c8;
	state->pdata.tclk_postcnt   = 0x00000008;
	state->pdata.ths_trailcnt   = 0x00000002;
	state->pdata.hstxvregcnt    = 0x00000005;
#else
//	state->pdata.pll_fbd        = 88;

	// timing setting
//	state->pdata.lineinitcnt    = 0x00001770;
//	state->pdata.lptxtimecnt    = 0x00000005;
//	state->pdata.tclk_headercnt = 0x00002004;
//	state->pdata.tclk_trailcnt  = 0x00000001;
//	state->pdata.ths_headercnt  = 0x00000606;
//	state->pdata.twakeup        = 0x00004a38;
//	state->pdata.tclk_postcnt   = 0x00000008;
//	state->pdata.ths_trailcnt   = 0x00000005;
//	state->pdata.hstxvregcnt    = 0x00000005;
//#endif

	state->pdata.pll_fbd        = 176;//144

	// timing setting
//case 972000000U:
	state->pdata.lineinitcnt = 0x1d01;//
	state->pdata.lptxtimecnt = 0x008;//
		/* tclk-preparecnt: 6, tclk-zerocnt: 45 */
	state->pdata.tclk_headercnt = 0x2D06;//0x0218
	state->pdata.tclk_trailcnt = 0x09;//
		/* ths-preparecnt: 7, ths-zerocnt: 17 */
	state->pdata.ths_headercnt = 0xd06;//0x0220
	state->pdata.twakeup = 0x4883;//
	state->pdata.tclk_postcnt = 0x010;//
	state->pdata.ths_trailcnt = 0xA;//
	state->pdata.hstxvregcnt = 5;//5
#endif



	//~ state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
						    //~ GPIOD_OUT_LOW);
	//~ if (IS_ERR(state->reset_gpio)) {
		//~ dev_err(dev, "failed to get reset gpio\n");
		//~ ret = PTR_ERR(state->reset_gpio);
		//~ goto disable_clk;
	//~ }

	if (state->reset_gpio) {
		pr_info("Calling reset GPIO but NOT IMPLEMENTED!");
		tc358743_gpio_reset(state);
	}
	ret = 0;
	goto free_endpoint;

disable_clk:
	// clk_disable_unprepare(refclk);
free_endpoint:
	v4l2_fwnode_endpoint_free(&endpoint);
put_node:
	of_node_put(ep);
	return ret;
}
#else
static inline int tc358743_probe_of(struct tc358743_state *state)
{
	return -ENODEV;
}
#endif

static int tc358743_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
	return 0;
}

static const struct v4l2_subdev_internal_ops tc358743_subdev_internal_ops = {
	.open = tc358743_open,
};

static const struct media_entity_operations tc358743_media_ops = {
	.link_validate = v4l2_subdev_link_validate,
};


static const struct regmap_config sensor_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.cache_type = REGCACHE_RBTREE,
};

static int tc358743_probe(struct i2c_client *client)
{
	static struct v4l2_dv_timings default_timing = V4L2_DV_BT_CEA_1920X1080P60;
    struct v4l2_subdev_edid sd_edid = {
		.blocks = 2,
		.edid = edid,
	};
	struct tc358743_state *state;
	struct tc358743_platform_data *pdata = client->dev.platform_data;
	struct v4l2_subdev *sd;
	u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
	int err;
	u16 chip_id_val;

    // pr_info("%s %s %s\n",__FUNCTION__,__DATE__,__TIME__);

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
		return -EIO;
	v4l_dbg(1, debug, client, "chip found @0x%x (%s)\n",
		client->addr, client->adapter->name);

	state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
			GFP_KERNEL);
	if (!state)
		return -ENOMEM;
    if (client->dev.of_node) {
        if (!tc358743_parse_dt(&state->pdata, client)) {
            pr_err("Couldn't parse device tree\n");
            return -ENODEV;
        }
    }

	state->i2c_client = client;

	/* platform data */
	if (pdata) {
		state->pdata = *pdata;
		pdata->endpoint.bus.mipi_csi2.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
	} else {
		err = tc358743_probe_of(state);
		if (err == -ENODEV)
			v4l_err(client, "No platform data!\n");
		if (err)
			return err;
	}

	sd = &state->sd;
	v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
	v4l2_info(sd,"Subdev init done\n");
	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;

	/* i2c access */
	chip_id_val = i2c_rd16(sd, CHIPID);
	v4l2_info(sd,"Chip ID val: %d\n", chip_id_val);

	if ((chip_id_val & MASK_CHIPID) != 0 || chip_id_val == 99) {
        v4l2_info(sd,"tc358743: ERROR: not a TC358743 on address0x%x\n",
			  client->addr);
		return -ENODEV;
	}

	/* control handlers */
	v4l2_ctrl_handler_init(&state->hdl, 3);
	v4l2_info(sd, "ctrl handler initied\n");

	/* private controls */
	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
			V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);

	/* custom controls */
	state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
			&tc358743_ctrl_audio_sampling_rate, NULL);

	state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
			&tc358743_ctrl_audio_present, NULL);

	v4l2_info(sd, "A bunch of new cutoms done\n");

	sd->ctrl_handler = &state->hdl;
	if (state->hdl.error) {
		err = state->hdl.error;
		goto err_hdl;
	}

	if (tc358743_update_controls(sd)) {
		err = -ENODEV;
		goto err_hdl;
	}

	v4l2_info(sd, "Controls updated\n");

	/* work queues */
	state->work_queues = create_singlethread_workqueue(client->name);
	if (!state->work_queues) {
		v4l2_err(sd, "Could not create work queue\n");
		err = -ENOMEM;
		goto err_hdl;
	}
	v4l2_info(sd, "Work queue created\n");

	state->pad.flags = MEDIA_PAD_FL_SOURCE;
	// sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR; //do not specify for tegra_media_entity_init?
	sd->entity.ops = &tc358743_media_ops;
	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;

#ifdef TC358743_VOUT_RGB
	state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
#else
	state->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_1X16;
#endif

	v4l2_info(sd, "About to call tegra_media_entity_init\n");
	err = tegra_media_entity_init(&sd->entity, 1, &state->pad, true, true);
	if (err < 0)
		goto err_hdl;
	v4l2_info(sd, "tegra_media_entity_init complete\n");

	v4l2_info(sd, "Set mbus_fmt_code in probe to: %d\n", state->mbus_fmt_code);

	sd->dev = &client->dev;
	v4l2_info(sd, "About to register subdev\n");
	err = v4l2_async_register_subdev(sd);
	v4l_dbg(1, debug, client, "Register subdev: %d\n", err);

	if (err < 0)
		goto err_hdl;

	mutex_init(&state->confctl_mutex);

	INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
			tc358743_delayed_work_enable_hotplug);

#ifdef CONFIG_VIDEO_TC358743_CEC
	v4l2_info(sd, "before cec_allocate_adapter\r\n");

	state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
		state, dev_name(&client->dev),
		CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
	if (IS_ERR(state->cec_adap)) {
		err = PTR_ERR(state->cec_adap);
		goto err_hdl;
	}
	irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;

	v4l2_info(sd, "after cec_allocate_adapter\r\n");
#endif

	v4l2_info(sd,"before tc358743_initial_setup\r\n");
	//tc358743_log_status(sd);
	tc358743_initial_setup(sd);
	v4l2_info(sd,"after tc358743_initial_setup\r\n");

	v4l2_info(sd,"before tc358743_s_dv_timings\r\n");
	//tc358743_log_status(sd);
	tc358743_s_dv_timings(sd, &default_timing);

	tc358743_set_csi_color_space(sd);

	v4l2_info(sd,"before tc358743_init_interrupts, irq: %d\r\n", state->i2c_client->irq);
	//tc358743_log_status(sd);
	tc358743_init_interrupts(sd);
	v4l2_info(sd,"after tc358743_init_interrupts, irq: %d\r\n", state->i2c_client->irq);
	if (state->i2c_client->irq) {
		v4l2_info(sd,"IQR request\r\n");
		err = devm_request_threaded_irq(&client->dev,
						state->i2c_client->irq,
						NULL, tc358743_irq_handler,
						IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
						"tc358743", state);
		v4l2_err(sd,"err, %d\n", err);
		if (err)
			goto err_work_queues;
	} else {
		INIT_WORK(&state->work_i2c_poll,
			  tc358743_work_i2c_poll);
		timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
		state->timer.expires = jiffies +
				       msecs_to_jiffies(POLL_INTERVAL_MS);
		add_timer(&state->timer);
	}

	err = cec_register_adapter(state->cec_adap, &client->dev);
	if (err < 0) {
		pr_err("%s: failed to register the cec device\n", __func__);
		cec_delete_adapter(state->cec_adap);
		state->cec_adap = NULL;
		goto err_work_queues;
	}

	tc358743_enable_interrupts(sd, true);
	i2c_wr16(sd, INTMASK, ~irq_mask);

	err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
	if (err)
		goto err_work_queues;

	v4l2_info(sd, "%s found @0x%x (%s)\n", client->name,
		  client->addr, client->adapter->name);
	tc358743_s_edid(sd, &sd_edid);
	tc358743_g_edid(sd, &sd_edid);

	tc358743_log_status(sd);
	v4l2_info(sd,"Probe complete\n");

	return 0;

err_work_queues:
	cec_unregister_adapter(state->cec_adap);
	if (!state->i2c_client->irq)
		flush_work(&state->work_i2c_poll);
	cancel_delayed_work(&state->delayed_work_enable_hotplug);
	destroy_workqueue(state->work_queues);
	mutex_destroy(&state->confctl_mutex);
err_hdl:
	media_entity_cleanup(&sd->entity);
	v4l2_ctrl_handler_free(&state->hdl);
	return err;
}

static int tc358743_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct tc358743_state *state = to_state(sd);

	if (!state->i2c_client->irq) {
		del_timer_sync(&state->timer);
		flush_work(&state->work_i2c_poll);
	}
	cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
	cec_unregister_adapter(state->cec_adap);
	destroy_workqueue(state->work_queues);
	v4l2_async_unregister_subdev(sd);
	v4l2_device_unregister_subdev(sd);
	mutex_destroy(&state->confctl_mutex);
	media_entity_cleanup(&sd->entity);
	v4l2_ctrl_handler_free(&state->hdl);

	return 0;
}

static const struct i2c_device_id tc358743_id[] = {
	{"tc358743", 0},
	{}
};

MODULE_DEVICE_TABLE(i2c, tc358743_id);

#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tc358743_of_match[] = {
	{ .compatible = "tc358743" },
	{},
};
MODULE_DEVICE_TABLE(of, tc358743_of_match);
#endif

static struct i2c_driver tc358743_driver = {
	.driver = {
		.name = "tc358743",
		.of_match_table = of_match_ptr(tc358743_of_match),
	},
	.probe_new = tc358743_probe,
	.remove = tc358743_remove,
	.id_table = tc358743_id,
};

module_i2c_driver(tc358743_driver);

Yes, this dual camera setup has worked w/Jetson Nano and Jetson Xavier - which is why the Orin was the next logical step. However, I wasn’t prepared for how challenging the move to JP5 on an Ubuntu 20 system has been.

I will attempt the changes fo csi5_fops.c

the csi setting fops need to be modify to adapt the tc358743, offical driver do not support nessecery property.

Hello k.fudong,

From your post (above) you made the following changes to csi5_fops.c :

I chang the csi5_fops.c to add a mipi_clock_rate_hz param after the lane_polarity pram in the csi5_stream_set_config function. and cil_config.mipi_clock_rate = mipi_clock_rate / 1000; so the csi cil_cil_config get the right mipi_clock_rate ;

If I understand that correctly, in csi5_stream_set_config() you added:

        unsigned int cil_settletime = 0;
        unsigned int lane_polarity = 0;

        unsigned int mipi_clock_rate_hz = 0;
        unsigned int index = 0;
        int vi_port = 0;

Then later in the code :

        if (s_data && !chan->pg_mode)
                /* jdc - orig lilne  cil_config.mipi_clock_rate = read_mipi_clk_from_dt(chan) / 1000; */
                cil_config.mipi_clock_rate = mipi_clock_rate_hz / 1000;
        else
                cil_config.mipi_clock_rate = csi->clk_freq / 1000;

Did I assume correctly that you meant mipi_clock_rate_hz / 1000 (and not mipi_clock_rate /1000) ?

Also - where does mipi_clock_rate_hz get set ? Is it from the .dtsi for the tc358743 ?

Thank you