Orin Nano Carrier Board PCIE#_CLKREQ pin at boot up


I have question on how the PCIE#_CLKREQ is expected to behave on carrier board at power up.
We are using the Orin Nano Dev Kit, and have a M.2 adaptor card for the Wi-Fi plugged in. We have the JetPack 6.0 image flashed to the dev kit.

When probing the lines ( CH1 [yellow] : VDD_CM , CH2 [blue] : VDD_3V3_SYS , CH3 [purple] : PCIE1_CLKREQ) at power-up on the dev kit (by power up we plug in the DC jack), we see this voltage step present on the PCIE1_CLKREQ line (CH3, purple). This pin is an open-drain bi-dir pin and has an internal pullup resistor to 3V3 on SoM, and at POR, the pin state is high-Z according to the pinmux spread sheet. Thus, there shouldn’t be an intermediate voltage as seen in the scope shot below on the PCIE1_CLKREQ. This intermediate voltage is approximately ~2.1V.

[Power up test]

Just to isolate that the M.2 Wi-Fi card is not pulling the line to an intermediate voltage, PCIE1_CLKREQ was measured with the M.2 adapter removed, yet the line still exhibited the same issue, and thus this step voltage is coming somewhere in the SoM / pin.

[Power up test without Wi-Fi M.2 card]

What is more interesting with the line is that depending on the board thermal condition, the length of the intermediate voltage increases. Below sequence of scope shots shows as the SoM heats up, the length of the intermediate voltage increases. In the end, the voltage remains flat at ~2V and will never reach 3V3 anymore. This will be an issue since VIH for 3V3 open-drain pin on SoC is min 2.475V.

[Power up with increasing board thermal]

Based on the above tests, my conclusion is that this is due to something within the SoM / SoC pin , and thus wanted to reach out if this step voltage seen is an expected behavior or not. I am wondering if there is any pull-down resistor / FET that gets enabled at boot up , and if so where I can find this information in the document.

Hi, could you help clarify what the thermal condition is in you test?


I don’t have a value for temperature or rime, but basically what i did is to remove the fan from the dev kit and let the SoC warm up for 10~30 seconds after boot, and then measure the signals on next power cycle.

Why is the PCIE1_CLKREQ* pulled to low? It should be kept high after power on since no device/request.


In the first image, I have a M.2 Wifi card attached and thus there is a device connected.
If you look at the 2nd image i posted, the line stays higher here since I removed the M.2 card for this test. Regardless of the device availability, you can see a step in the voltage for PCIE1_CLKREQ.

I mean it drops to zero in all your image, why? The pin has pull-up on module, it should be high.


PCIE_CLKREQ is the purple line in the scope shot.
For tests where I have a WiFi module M.2 card, it will be pulled down to request the clock to start the PCIe protocol since the device is connected.

If you look at the 2nd image in my post (I am attaching it here as well) which doesn’t have M.2 card attached, the line stays high all of the time due to the internal pullup. My question is the initial step you see which is ~2V. This line should only have internal pullup to 3V3 so I want to know why this intermediate voltage exists and where the source is from on the SoM.

The pin is a 1.8V pin and 3.3V tolerance enabled. So the intermediate voltage is caused by the timing of 1.8V and 3.3V.


I see, and the reason the intermediate voltage is ~2.1V is because there is reverse leakage from the 3V3 pullup-resistor on SoM to the 1V8 CMOS logic via the high side FET body diode?

If above is the case, does that mean the 3V3 tolerance is not properly being enabled by the SoC when the line stays at ~2.1V ?


Is there an update on this item?

Hello @Trumany ,

Checking in to see if there is any update on this.
Two things I would like to get confirmations are :

  1. Reason for the intermediate voltage being ~2.1V is due to the leakage from 3V3 pullup to the 1v8 CMOS logic supply?
  2. For cases where the line stays at ~2.1V, is 3V3 tolerance not being enabled properly?


Have you tried to changed the pinmux setting for PCIE1_CLKREQ by using pinmux spreadsheet and see if behavior is changed?


I haven’t tested on the exact same pin with the dev kit, but I have tested this with a different nCLKREQ signal (PCIE3_CLKREQ* , SODIMM Pin# 225) . This pin was configured as an input GPIO (GPIO3_PAG.04) and I have observed the same behavior with the intermediate voltage. Pinmux attached for reference.

Attached below is the scope shot for this signal when configured as an input. CH4 (dark blue) is the signal of interest, other signals are from the custom carrier board so it can be ignored. Notice how the intermediate voltage is present (this is also at boot up)

Hi, could you probe this pin by setting the pin as “Output” and “Drive 0”? That could show the timing of pinmux setting start work on your board. And also probe the pin PCIE1_CLKREQ since PCIE3 is not supported as PCIe port on Orin nano.

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