Orin Nano PCIE Clock turning off

[matt.read]

Hello I am using the 8G Orin Nano on a Custom carrier board. We are using an FPGA on PCIE0 which on the dev kit is the M.2m (x4 NVMe):

We are unable to see the FPGA with “lspci”. When we scope our clock with a diff probe on PCIE0_CLK_P and PCIE0_CLK_N it comes on when the Orin boots but turns off a few seconds later.

I think the default behavior is if there is no PCIe endpoint detected, it powers down the PCIe controller and therefore the clock.

For Debug purposes (to do an eye diagram of the clock) I need it to stay on. I have tried to modify the tegra_pcie_port_check_link function in the pci-tegra.c and recompiled the pcie-tegra194.ko module, but my clock still turns off.

I have modified the tegra_pcie_port_check_link to always return true after the retries:

#define TEGRA_PCIE_LINKUP_TIMEOUT	200	/* up to 1.2 seconds */
static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
{
	struct device *dev = port->pcie->dev;
	unsigned int retries = 3;
	unsigned long value;

	dev_dbg(dev, "PCIe_TEST: Clock to stay on even if no detected endpoints");

	/* override presence detection */
	value = readl(port->base + RP_PRIV_MISC);
	value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
	value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
	writel(value, port->base + RP_PRIV_MISC);

	do {
		unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;

		do {
			value = readl(port->base + RP_VEND_XP);

			if (value & RP_VEND_XP_DL_UP)
				break;

			usleep_range(1000, 2000);
		} while (--timeout);

		if (!timeout) {
			dev_dbg(dev, "link %u down, retrying\n", port->index);
			goto retry;
		}

		timeout = TEGRA_PCIE_LINKUP_TIMEOUT;

		do {
			value = readl(port->base + RP_LINK_CONTROL_STATUS);

			if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
				return true;

			usleep_range(1000, 2000);
		} while (--timeout);

retry:
		tegra_pcie_port_reset(port);
	} while (--retries);
	return true;
}

Would anyone know to why my clock might still turn off?

[WayneWWW]

I don’t think you need to debug this NVIDIA driver. Most cases that lead to FPGA not enumerated is on the FPGA side but not Jetson side.

Are you sure FPGA state is ready when PCIe RST de-asserted?