Hi NV,
we design a new carrier board and do “HDMI TMDS Source Compliance Test” but fail,
fail item is HF1-55, it about “HDMI DDC setup time”, does it can be adjusted?
SDK version is L4T 36.4.3,
thanks.
HF1-55 is link layer signal. We are only in control of the PHY signal on Orin SOC side.
For HDMI DDC signal, we cannot capture the tsu_start signal, we only test tsu_data signal. Please make sure your schematics and layout meets our design guide requirements. This is not required and could be waived.
Hi NV,
Do you mean HF1-55 could be waived? but as i know, HF1-55 is the required items and must be PASS. we tried to adjusted the pull up resistor on SCL/SDA, but the tSU:STA still fail, please see attached waveform, is there any way to delay SDA high to low timing by SW? or can we adjust the CLK from 100kHz to 400kHz?
Hi NV,
Is there anything feedback on this issue?
we are stuck on this to get HDMI logo currently.
kindly let me know if you have any suggestion.
we are still checking this.
Hi Sir,
Any update for this issue?
Can we adjust set-up time by some register?
Thanks.

