# Orin NX SPI delay between transfers

**URL:** <https://forums.developer.nvidia.com/t/orin-nx-spi-delay-between-transfers/265234>\
**Category:** Jetson Orin NX\
**Tags:** spi, nvbugs\
**Created:** [September 1, 2023, 3:37pm UTC](https://forums.developer.nvidia.com/t/orin-nx-spi-delay-between-transfers/265234 "2023-09-01T15:37:44Z")\
**Posts on this page:** 1\
**Showing post:** 21

<div class="post-metadata">

**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\
**Post date:** [October 26, 2023, 6:20am UTC](https://forums.developer.nvidia.com/t/orin-nx-spi-delay-between-transfers/265234/21 "2023-10-26T06:20:03Z")

</div>

Could you help to apply the following patch on K5.10 driver and compare the result?

```auto
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -174,6 +174,7 @@
 #define SPI_TX_FIFO_UNF_FATAL_INTR_EN BIT(27)
 #define SPI_TX_FIFO_OVF_FATAL_INTR_EN BIT(28)
 #define SPI_FATAL_INTR_ALL_EN_0 (0x1fUL << 25)
+#define AUTOSUSPEND_TIMEOUT 300 /* in millisec */
 
 struct tegra_spi_soc_data {
 	bool has_intr_mask_reg;
@@ -1348,7 +1349,8 @@ static int tegra_spi_setup(struct spi_device *spi)
 		tegra_spi_set_cmd2(spi, spi->max_speed_hz);
 	spin_unlock_irqrestore(&tspi->lock, flags);
 
-	pm_runtime_put(tspi->dev);
+	pm_runtime_mark_last_busy(tspi->dev);
+	pm_runtime_put_autosuspend(tspi->dev);
 	return 0;
 }
 
@@ -1405,7 +1407,8 @@ static int tegra_spi_cs_low(struct spi_device *spi, bool state)
 	}
 
 	spin_unlock_irqrestore(&tspi->lock, flags);
-	pm_runtime_put(tspi->dev);
+	pm_runtime_mark_last_busy(tspi->dev);
+	pm_runtime_put_autosuspend(tspi->dev);
 	return 0;
 }
 
@@ -1959,7 +1962,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
 			goto exit_tx_dma_free;
 		}
 	}
-
+	pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
+	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 	if (!pm_runtime_enabled(&pdev->dev)) {
 		ret = tegra_spi_runtime_resume(&pdev->dev);
@@ -1988,7 +1992,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
 	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
 	tspi->command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_mark_last_busy(&pdev->dev);
+	pm_runtime_put_autosuspend(&pdev->dev);
 	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
 				   tegra_spi_isr_thread, IRQF_ONESHOT,
 				   dev_name(&pdev->dev), tspi);
@@ -2015,6 +2020,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
 		tegra_spi_runtime_suspend(&pdev->dev);
 	if (tspi->clock_always_on)
 		clk_disable_unprepare(tspi->clk);
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
 exit_tx_dma_free:
 	tegra_spi_deinit_dma_param(tspi, false);
 exit_rx_dma_free:
@@ -2086,7 +2092,8 @@ static int tegra_spi_resume(struct device *dev)
 	tspi->last_used_cs = ctrl->num_chipselect + 1;
 	tegra_spi_set_intr_mask(tspi);
 	tegra_spi_set_fatal_intr_en(tspi);
-	pm_runtime_put(dev);
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
 
 	return spi_controller_resume(ctrl);
 }

```

---

_[View the full topic](https://forums.developer.nvidia.com/t/orin-nx-spi-delay-between-transfers/265234)._