Orin NX USB 3-2 enable question

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin NX
1

I have noticed different information in the USB documentation on updating the DTB file. I’ve normally been manually editing the DTB and recompiling it.

For the USB 3-1 section it calls out a phandle = <0xee>

for USB3-2 section is disabled

All the notes in the online documents on board USB adaptation do not show the phandle value called out.
for example from the orin NX adaptation for JetPack 6…
--------------- This is from the online documents --------------------------------
xusb_padctl: padctl@3520000 {
…
pads {
usb2 {
lanes {
usb2-0 {
nvidia,function = “xusb”;
status = “okay”;
};
…
};
};
usb3 {
lanes {
…
usb3-1 {
nvidia,function = “xusb”;
status = “okay”;
};
…
};
};
};
ports {
usb2-0 {
mode = “otg”;
usb-role-switch;
vbus-supply = <&vdd_5v0_sys>;
status = “okay”;
port {
hs_typec_p1: endpoint {
remote-endpoint = <&hs_ucsi_ccg_p1>;
};
};
};
…
usb3-1 {
nvidia,usb2-companion = <0>;
status = “okay”;
port {
ss_typec_p1: endpoint {
remote-endpoint = <&ss_ucsi_ccg_p1>;
};
};
};
…
};
};
---------------------------------------------------------------------------- This is from flashing the Orin NX with JP 6.0
padctl@3520000 {
compatible = “nvidia,tegra234-xusb-padctl”;
reg = <0x00 0x3520000 0x00 0x20000 0x00 0x3540000 0x00 0x10000>;
reg-names = “padctl\0ao”;
interrupts = <0x00 0xa7 0x04>;
resets = <0x03 0x72>;
reset-names = “padctl”;
status = “okay”;
vclamp-usb-supply = <0xe7>;
avdd-usb-supply = <0xe8>;
phandle = <0xec>;

		pads {

			usb2 {
				clocks = <0x03 0xa5>;
				clock-names = "trk";

				lanes {

					usb2-0 {
						nvidia,function = "xusb";
						status = "okay";
						#phy-cells = <0x00>;
						phandle = <0xed>;
					};

					usb2-1 {
						nvidia,function = "xusb";
						status = "okay";
						#phy-cells = <0x00>;
						phandle = <0xef>;
					};

					usb2-2 {
						nvidia,function = "xusb";
						status = "okay";
						#phy-cells = <0x00>;
						phandle = <0xf0>;
					};

					usb2-3 {
						nvidia,function = "xusb";
						status = "disabled";
						#phy-cells = <0x00>;
					};
				};
			};

			usb3 {

				lanes {

					usb3-0 {
						nvidia,function = "xusb";
						status = "okay";
						#phy-cells = <0x00>;
						phandle = <0xf1>;
					};

					usb3-1 {
						nvidia,function = "xusb";
						status = "okay";
						#phy-cells = <0x00>;
						phandle = <0xee>;
					};

					usb3-2 {
						nvidia,function = "xusb";
						status = "disabled";
						#phy-cells = <0x00>;	
					};

					usb3-3 {
						nvidia,function = "xusb";
						status = "disabled";
						#phy-cells = <0x00>;
					};
				};
			};
		};

I also notice that the phys addresses are called out in the file as well after flashing the board…shown below

	usb@3610000 {
		compatible = "nvidia,tegra234-xusb";
		reg = <0x00 0x3610000 0x00 0x40000 0x00 0x3600000 0x00 0x10000 0x00 0x3650000 0x00 0x10000>;
		reg-names = "hcd\0fpci\0bar2";
		interrupts = <0x00 0xa3 0x04 0x00 0xa4 0x04>;
		clocks = <0x03 0x10b 0x03 0x10d 0x03 0x10c 0x03 0x113 0x03 0x0e 0x03 0x110 0x03 0x67 0x03 0x0e 0x03 0x64>;
		clock-names = "xusb_host\0xusb_falcon_src\0xusb_ss\0xusb_ss_src\0xusb_hs_src\0xusb_fs_src\0pll_u_480m\0clk_m\0pll_e";
		interconnects = <0x50 0x4a 0x51 0x50 0x4b 0x51>;
		interconnect-names = "dma-mem\0write";
		iommus = <0xe2 0x0e>;
		power-domains = <0x03 0x0c 0x03 0x0a>;
		power-domain-names = "xusb_host\0xusb_ss";
		nvidia,xusb-padctl = <0xec>;
		dma-coherent;
		status = "okay";
		phys = <0xed 0xef 0xf0 0xf1 0xee>;
		phy-names = "usb2-0\0usb2-1\0usb2-2\0usb3-0\0usb3-1";
	};

This is from the adaptation manual
usb@3610000 {
…
phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
phy-names = “usb2-0”, “usb3-1”;
nvidia,xusb-padctl = <&xusb_padctl>;
status = “okay”;
…
};

Can you tell me where to find the proper information to modify the DTB file to enable the USB 3-2 port.
I am the only one in my organization working on this and I have limited knowledge of the device tree. I’ve been reading everything you have online but haven’t had success in enabling USB3-2

Thank you

3

I am not quite sure what is your exact question here.

Are you saying that you don’t know what is “phandle” doing in the device tree?

If that is your question then it may not have anything to do with documentation, it is really that you are not familiar with device tree. Phandle is created during compilation. You won’t see it in original source code.

If you want usb3-2 to be enabled and you saw it is disabled in the device tree, then it is time you should set it to enabled.

4

You are correct, I’m not that familiar with editing the device tree. Reading up on it.
What file would you edit to enable USB3-2 prior to creating/compiling the device tree?

5

What is the original DTS file that you would edit to set USB3-2 to enabled and then use the dtc compiler?

6

I think you could start from the beginning first. Device tree structure is standard Linux kernel syntax.

And for Jetson, you could check /boot/dtb on your board to know what is the default dtb in use there. And then you could go back to source code and know which file is in use. Find that file out and then you could trace down the other code there.

It is actually no precise answer to say “you must enable USB3-2 in xxx file” when you know how device tree syntax works. For example, I can add it in multiple locations and their result could be same in the end.

7

Hi Wayne,
Thank you very much for pointing me in a direction. I’ll start the learning…

8

Wayne,
Been doing a lot of digging. Can you give me a hint on which dtsi source file references the USB3 callouts to get enabled. I have found it to be quite a nesting of DTS files. The .yaml files didn’t point me anywhere. There is a generic file that calls out all the USB ports but somewhere that is modified when you do the DTB compile.

9

Have you checked /boot/dtb on your board to know where to start first? If you didn’t do that first, then it would be hard to start…

10

Yes, I did start there. I also found in the /source/hardware what looks like the Orin Devkit dtsi file that calls out all the generic phy addresses variables for all the USB. What I’m missing is the schema or config file that takes that base dtsi and enables/disables stuff to generate the final dts file that is compiled into the dtb. I’m close, just missing that one piece where I believe I can set USB3-2 to be okay and it will be generated during the DTB compile.
Can you tell me which files or folders in the source I should be looking at?

11

The document for NVIDIA USB driver device tree configuration is over here.

You could start from ./nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi