Orin pcie c4正常,c1无法加载

c1连接5g模组 rst脚量没有被拉高,c4挂载了ssd正常被拉高,已按照指导将PEX_C1_RST_N和PEX_C1_CLKREQ_N配置pinmux,与c4的值一致,设备树中也使能了pcie,请问rst脚没有拉高会是什么导致?
pex_l0_clkreq_n_pk0 {
nvidia,pins = “pex_l0_clkreq_n_pk0”;
nvidia,function = “pe0”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

		pex_l0_rst_n_pk1 {
			nvidia,pins = "pex_l0_rst_n_pk1";
			nvidia,function = "pe0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
		};

//TEGRA234_MAIN_GPIO(K, 0)
//TEGRA234_MAIN_GPIO(K, 1)

請問到底在問C1還是C0?

你改的pinmux完全是給C0在用的…

是c1,我看pinmux表里顺序是乱的,c1对应的是l0

那個是C0. 請參考後面的表格中的controller 號碼決定

硬件设计中5g pcie用的是c1,连接的是D9和B9,这块有问题吗?
image

你的意思这个pcie 5g连得是c0,我应该配pcie@14180000控制器吗?

對, 這樣的設計有問題 請更改

请问如果要用C0,是要修改ODMDATA hsio-uphy-config-0为hsio-uphy-config-16吗?如果需要修改的话是不是会影响这路usb3.0呢?
image

是的 需要修改, 改完之後USB3.2(p0)就無法使用

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.