ORIN uses RGMII to connect phy 88E1512, the network link is unavailable

[WayneWWW]

As our document indicates, pe6 ~ pf3 should set nvidia,pull different from yours. That is what I kept asking but you didin’t answer…

[chinaoak]

Thanks a lot! I’ll try.

[sunzhzh]

Can this document be shared? We have always referred to the Adaptation and Bringup. We don’t know whether there are any updates, but we can’t find them in the download center

[WayneWWW]

please check

https://developer.nvidia.com/adaptation-and-bringup-jetson-agx-orinpdf

[chinaoak]

Still can’t work, any other suggestion?

		eqos_rd0_pe6 {
			nvidia,pins = "eqos_rd0_pe6";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd1_pe7 {
			nvidia,pins = "eqos_rd1_pe7";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};
		eqos_rd2_pf0 {
			nvidia,pins = "eqos_rd2_pf0";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd3_pf1 {
			nvidia,pins = "eqos_rd3_pf1";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rx_ctl_pf2 {
			nvidia,pins = "eqos_rx_ctl_pf2";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rxc_pf3 {
			nvidia,pins = "eqos_rxc_pf3";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

[chinaoak]

Hi, I use ethtool and mdio tool get these mesage.
is the net driver using nvethernet?
all the registers values are the reset default, and the phyid is correct, what can be the reason?

[sunzhzh]

Our hardware design is based on the AGX Xavier development kit, but there is a problem. In the Xavier development kit, Xavier RGMII to PHY RGMII is tx connected to tx, rx connected to rx, and in Xavier’s pinmux, TX is output, RX is input. For PHY, tx is RGMII Transmit Data, and rx is RGMII Receive Data. So shouldn’t cross connect?

[sunzhzh]

I’m sorry, maybe I read it wrong