Parasitic capacitance of the TX2 I2C bus

Is there any way to know or calculate the parasitic capacitance of the I2C buses of the TX2? I’ve searched in the datasheet and TRM but yet no clue.

Hi, do you meet any issue on this? How many devices do you want to attach on one I2C? Generally the total load cap should be less than 400pF, it will have no problem for most usage.

I think the question is, what is the JETSON’s add to the total cap.
To shun rise time issues with higher speed of I2C such es 1M, parallel capacitors to the pull up resistors can help.