PCA9555 interrupt question on Jetson Nano

I’m testing PCA9555 on Jetson Nano board. It connects to I2C0 interface and PCA9555 INT pin connects to GPIO07_LS of J41.
The following is my devicetree configuration.
i2c@7000c000 {
#address-cells = <0x1>;
#size-cells = <0x0>;

pca9555_1:gpio@20 {
compatible = “nxp,pca9555”;
reg = <0x20>;
gpio-controller;
#gpio-cells = <0x2>;
pinctrl-names = “default”;
pinctrl-0 = <>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x56>;
interrupts = <0xa8 0x0>;
vcc-supply = <0x41>;
status = “okay”;
}

}

The system starts up. I input the command ‘cat /proc/interrupts | grep GPIO’,
and find that the GPIO07_LS interrupt count increases all the time until it up to 200001.
Then the console will print the following error information.

root@localhost:~# cat /proc/interrupts | grep GPIO
267: 110256 0 0 0 GPIO 168 Level 0-0020
288: 0 0 0 0 GPIO 189 Edge Power
289: 0 0 0 0 GPIO 190 Edge Forcerecovery
300: 0 0 0 0 GPIO 201 Edge sdhci-tegra.0 cd
301: 0 0 0 0 GPIO 202 Edge pwm-fan-tach
324: 0 0 0 0 GPIO 225 Edge tegradc.0
327: 0 0 0 0 GPIO 228 Edge extcon:extcon@1

root@localhost:~# cat /proc/interrupts | grep GPIO
267: 200001 0 0 0 GPIO 168 Level 0-0020
288: 0 0 0 0 GPIO 189 Edge Power
289: 0 0 0 0 GPIO 190 Edge Forcerecovery
300: 0 0 0 0 GPIO 201 Edge sdhci-tegra.0 cd
301: 0 0 0 0 GPIO 202 Edge pwm-fan-tach
324: 0 0 0 0 GPIO 225 Edge tegradc.0
327: 0 0 0 0 GPIO 228 Edge extcon:extcon@1

[ 36.235152] irq 267: nobody cared (try booting with the “irqpoll” option)
[ 36.243559] CPU: 0 PID: 4141 Comm: NetworkManager Not tainted 4.9.140-tegra #79
[ 36.243562] Hardware name: NVIDIA Jetson Nano Developer Kit (DT)
[ 36.243565] Call trace:
[ 36.243575] [] dump_backtrace+0x0/0x198
[ 36.243580] [] show_stack+0x24/0x30
[ 36.243585] [] dump_stack+0x98/0xc0
[ 36.243591] [] __report_bad_irq+0x3c/0xf8
[ 36.243594] [] note_interrupt+0x2c8/0x318
[ 36.243598] [] handle_irq_event_percpu+0x50/0x60
[ 36.243601] [] handle_irq_event+0x50/0x80
[ 36.243605] [] handle_level_irq+0xb8/0x148
[ 36.243608] [] generic_handle_irq+0x34/0x50
[ 36.243612] [] tegra_gpio_irq_handler+0x134/0x1e8
[ 36.243615] [] generic_handle_irq+0x34/0x50
[ 36.243618] [] __handle_domain_irq+0x68/0xc0
[ 36.243621] [] gic_handle_irq+0x5c/0xb0
[ 36.243624] [] el0_irq_naked+0x54/0x60
[ 36.243626] handlers:
[ 36.245896] [] irq_default_primary_handler threaded [] pca953x_irq_handler
[ 36.251385] Disabling IRQ #267

hello ainolike,

please also refer to [3.3 GPIO Pins] of Nano datasheets.
please consider using the pin without “Alternate Function”.
thanks

Hi JerryChang,
In devicetree GPIO07_LS configuration as follows. How can I configure GPIO07_LS as interrupt function?
lcd_bl_pwm_pv0 {
nvidia,pins = “lcd_bl_pwm_pv0”;
nvidia,function = “rsvd3”;
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};

hello ainolike,

this pin, GPIO07 it has an alternate function as PWM.
may I know what’s the actual use-case to use this pin as interrupt function?

Hi JerryChang,
This pin connects to PCA9555 INT pin. It receives PCA9555 interrupt signal.

Hi JerryChang,
I use NV_Jetson_Nano_Module_Pinmux_Config_Template.xlsm generate the new tegra210-test1-gpio-default.dtsi and tegra210-test1-pinmux.dtsi. GPIO07 configuration is same as before. I think it has been configured as GPIO3_PV.00 function. It doesn’t use “Alternate Function”. GPIO07 configuration as follows.
Jetson Nano Signal Name–GPIO07
“B01SODIMM”---------------206
Ball Name-------------------LCD_BL_PWM
GPIO-------------------------GPIO3_PV.00
SFIO0------------------------
SFIO1------------------------PM3_PWM0
SFIO2------------------------
SFIO3------------------------
Wake------------------------
Strap------------------------
Pin State--------------------pd
Customer Usage------------GPIO3_PV.00
Pin Direction----------------Input
Req. Initial State------------Int PD
Wake Pin---------------------
Lock--------------------------
3.3V Tolerance Enable-------
Ext Pull Up Value (Ω)---------
Ext Pull Down Value (Ω)------
Req. Deep Sleep State-------

I have the same test with GPIO01, GPIO11, GPIO12, GPIO13, and I got the same result.

hello ainolike,

could you please confirm you’re including below for the GPIO interrupt pin.
for example,

    interrupt-parent = <&gpio>;
    interrupts = <TEGRA_GPIO(V, 0) 0x01>;     // IRQ_TYPE_EDGE_RISING	

BTW,
here’s IRQ bindings definitions for your reference,
for example,

#define IRQ_TYPE_NONE		0
#define IRQ_TYPE_EDGE_RISING	1
#define IRQ_TYPE_EDGE_FALLING	2
#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	4
#define IRQ_TYPE_LEVEL_LOW	8

Hi JerryChang,
I have modified my devicetree as follows and got the same result.

i2c@7000c000 {
#address-cells = <0x1>;
#size-cells = <0x0>;

pca9555_1:gpio@20 {
compatible = “nxp,pca9555”;
reg = <0x20>;
gpio-controller;
#gpio-cells = <0x2>;
pinctrl-names = “default”;
pinctrl-0 = <>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(V, 0) 0x0>;
vcc-supply = <0x41>;
status = “okay”;
}

}

hello ainolike,

this error might caused by updating IIR register during IER register writes.
could you please review your driver, please try have the implementation to not update status (i.e. IIR) during IER register writes.

BTW,
this might also the caused by the buggy hardware to generates spurious IRQs to software without setting any IRQ status,

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