PCI device tree node

Hello,

I’m trying to understand the device tree node of PCI and not sure how it is named. “pci@1,0”, what does ‘0’ mean? I can’t find anything about this in the device tree spec. “pci@0x800” would have been more meaningful as per spec, correct?

Next, how do I corelate the pins for “pci@1,0” and “pci@2,0” etc. from module? Will Jetson_Nano_Module_Pinmux_Config_Template_PreRelease file help? If so please explain with document reference. This will be helpful to know other parts of device tree construction.

Thanks,
Hakim

pcie@1003000 {
compatible = “nvidia,tegra210-pcie”, “nvidia,tegra124-pcie”;
power-domains = <0x78>;
device_type = “pci”;
reg = <0x0 0x1003000 0x0 0x800 0x0 0x1003800 0x0 0x800 0x0 0x11fff000 0x0 0x1000>;
reg-names = “pads”, “afi”, “cs”;
interrupts = <0x0 0x62 0x4 0x0 0x63 0x4>;
interrupt-names = “intr”, “msi”;
clocks = <0x26 0x46 0x26 0x48 0x26 0x107 0x26 0x12c 0x26 0x63>;
clock-names = “pex”, “afi”, “pll_e”, “cml”, “mselect”;
resets = <0x26 0x46 0x26 0x48 0x26 0x4a>;
reset-names = “pex”, “afi”, “pcie_x”;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
interrupt-map = <0x0 0x0 0x0 0x0 0x38 0x0 0x62 0x4>;
pinctrl-names = “clkreq-0-bi-dir-enable”, “clkreq-1-bi-dir-enable”, “clkreq-0-in-dir-enable”, “clkreq-1-in-dir-enable”, “pex-io-dpd-dis”, “pex-io-dpd-en”;
pinctrl-0 = <0x79>;
pinctrl-1 = <0x7a>;
pinctrl-2 = <0x7b>;
pinctrl-3 = <0x7c>;
pinctrl-4 = <0x7d>;
pinctrl-5 = <0x7e>;
bus-range = <0x0 0xff>;
#address-cells = <0x3>;
#size-cells = <0x2>;
ranges = <0x82000000 0x0 0x1000000 0x0 0x1000000 0x0 0x1000 0x82000000 0x0 0x1001000 0x0 0x1001000 0x0 0x1000 0x81000000 0x0 0x0 0x0 0x12000000 0x0 0x10000 0x82000000 0x0 0x13000000 0x0 0x13000000 0x0 0xd000000 0xc2000000 0x0 0x20000000 0x0 0x20000000 0x0 0x20000000>;
status = “okay”;
nvidia,wake-gpio = <0x5b 0x2 0x0>;
nvidia,pmc-wakeup = <0x3c 0x1 0x0 0x8>;
avdd-pll-uerefe-supply = <0x43>;
hvddio-pex-supply = <0x3b>;
dvddio-pex-supply = <0x44>;
dvdd-pex-pll-supply = <0x44>;
hvdd-pex-pll-e-supply = <0x3b>;
vddio-pex-ctl-supply = <0x3b>;

	pci@1,0 {
		device_type = "pci";
		assigned-addresses = <0x82000800 0x0 0x1000000 0x0 0x1000>;
		reg = <0x800 0x0 0x0 0x0 0x0>;
		status = "okay";
		#address-cells = <0x3>;
		#size-cells = <0x2>;
		ranges;
		nvidia,num-lanes = <0x4>;
		nvidia,afi-ctl-offset = <0x110>;
		nvidia,disable-aspm-states = <0xf>;
		phys = <0x7f 0x80 0x81 0x82>;
		phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
		nvidia,disable-clock-request;
	};

	pci@2,0 {
		device_type = "pci";
		assigned-addresses = <0x82001000 0x0 0x1001000 0x0 0x1000>;
		reg = <0x1000 0x0 0x0 0x0 0x0>;
		status = "okay";
		#address-cells = <0x3>;
		#size-cells = <0x2>;
		ranges;
		nvidia,num-lanes = <0x1>;
		nvidia,afi-ctl-offset = <0x118>;
		nvidia,disable-aspm-states = <0xf>;
		phys = <0x83>;
		phy-names = "pcie-0";
		nvidia,plat-gpios = <0x5b 0xbb 0x0>;

		ethernet@0,0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
		};
	};

There are only two PCIe controllers in T210. I’m wondering what is the confusing part for you here? I mean what pin names are confusing to you?

How do relate these to pci@1,0 and pci@2,0

PCIE0_RX3_N 155 PEX_RX1N
PCIE0_RX3_P 157 PEX_RX1P
PCIE0_TX3_N 154 PEX_TX1N
PCIE0_TX3_P 156 PEX_TX1P
PCIE0_RX2_N 149 PEX_RX2N
PCIE0_RX2_P 151 PEX_RX2P
PCIE0_TX2_N 148 PEX_TX2N
PCIE0_TX2_P 150 PEX_TX2P
PCIE0_RX1_N 137 PEX_RX3N
PCIE0_RX1_P 139 PEX_RX3P
PCIE0_TX1_N 140 PEX_TX3N
PCIE0_TX1_P 142 PEX_TX3P
PCIE0_RX0_N 131 PEX_RX4N
PCIE0_RX0_P 133 PEX_RX4P
PCIE0_TX0_N 134 PEX_TX4N
PCIE0_TX0_P 136 PEX_TX4P

Hi,

Please refer to the product design guide. It will tell how the pcie controller uses each pin.

Thanks.