# PCI-E bottleneck when transferring data between CPU and GPU

**URL:** <https://forums.developer.nvidia.com/t/pci-e-bottleneck-when-transferring-data-between-cpu-and-gpu/22200>\
**Category:** CUDA Programming and Performance\
**Created:** [April 28, 2011, 4:12am UTC](https://forums.developer.nvidia.com/t/pci-e-bottleneck-when-transferring-data-between-cpu-and-gpu/22200 "2011-04-28T04:12:19Z")\
**Posts on this page:** 3\
**Page:** 1

<div class="post-metadata">

**Author:** ![hjazz](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@hjazz](https://forums.developer.nvidia.com/u/hjazz)\
**Post date:** [April 28, 2011, 4:12am UTC](https://forums.developer.nvidia.com/t/pci-e-bottleneck-when-transferring-data-between-cpu-and-gpu/22200/1 "2011-04-28T04:12:19Z")

</div>

Hi,

I’ve read that the transfer overhead between CPU and GPU is a big bottleneck in achieving high performance in GPU/CPU applications. Why is this so?

According to Nvidia’s bandwidthtest program, my CPU/GPU bandwidth is about 4 to 5 GBps. Is this the peak performance, and actual performance is likely much lower? My application can only reach ~17 Gbps when data transfer is included in the performance measurement, a large drop from the 100+ Gbps rate when measuring only the GPU computation without data transfer.

Thank you.

Regards,  
Rayne

---

<div class="post-metadata">

**Author:** ![cbuchner1](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/cbuchner1/32/14168_2.png) [@cbuchner1](https://forums.developer.nvidia.com/u/cbuchner1)\
**Post date:** [April 28, 2011, 9:07am UTC](https://forums.developer.nvidia.com/t/pci-e-bottleneck-when-transferring-data-between-cpu-and-gpu/22200/2 "2011-04-28T09:07:42Z")

</div>

> [@](#):
>
> Hi,
> 
> I’ve read that the transfer overhead between CPU and GPU is a big bottleneck in achieving high performance in GPU/CPU applications. Why is this so?

a) Cost (of mainboards)

b) Physics

c) the fact that established bus systems like PCI-x are never at the forefront of what is technologically feasible.

---

<div class="post-metadata">

**Author:** ![avidday](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/avidday/32/59219_2.png) [@avidday](https://forums.developer.nvidia.com/u/avidday)\
**Post date:** [April 28, 2011, 9:43am UTC](https://forums.developer.nvidia.com/t/pci-e-bottleneck-when-transferring-data-between-cpu-and-gpu/22200/3 "2011-04-28T09:43:00Z")

</div>

> [@](#):
>
> c) the fact that established bus systems like PCI-x are never at the forefront of what is technologically feasible.

Small bit of terminology pedantry: PCI, PCI-X (PCI-eXtended), PCI-e (PCI-express). Confusingly similar acronyms, but not the same things.