PCI lane port mapping question

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX1
1

I am working on a custom carrier board and have a question about pci/usb port mapping. I have one mSATA mini PCIe one standard mini PCIe two USB 3.0 ports one USB OTG port and one regular USB 2.0 port. What would the correct mapping be for xusb?

in uboot my configuration lists this:
tegra-pcie: 2x1, 1x1 configuration:

from nv-tegra.nvidia Code Review - linux-3.10.git/blob - arch/arm/mach-tegra/include/mach/tegra_usb_pad_ctrl.h

33 /* Encode lane width of each RP in nibbles starting with RP0 at lowest */
34 #define PCIE_LANES_X4_X1 0x14
35 #define PCIE_LANES_X4_X0 0x04
36 #define PCIE_LANES_X2_X1 0x12
37 #define PCIE_LANES_X2_X0 0x02
38 #define PCIE_LANES_X0_X1 0x10

2

Hi Linuxforall,
Please check the information in:
[Tegra_Linux_Driver_Package_Documents_R24.2.1 → Start_L4T_Docs.html → Downloads → Platform Adaptation and Bring-Up Guide (PDF)]
https://developer.nvidia.com/embedded/dlc/l4t-documentation-24-2-1