PCIe BAR disabled on Jetson TX2 using Xilinx

I have a PCI card that when connected on to the TX2, shows thw following lspci output.

01:00.0 Serial controller: Xilinx Corporation Device 9024 (prog-if 01 [16450])
	Subsystem: Xilinx Corporation Device 0007
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 422
	Region 0: Memory at <unassigned> (64-bit, non-prefetchable) [disabled]
	Region 2: Memory at <unassigned> (64-bit, non-prefetchable) [disabled]
	Region 4: Memory at <unassigned> (64-bit, non-prefetchable) [disabled]
	Capabilities: <access denied>

But when I connect it to an x86, it shows the following.

1a:00.0 Serial controller: Xilinx Corporation Device 9024 (prog-if 01 [16450])
	Subsystem: Xilinx Corporation Device 0007
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 35
	Region 0: Memory at b0000000 (64-bit, non-prefetchable) 
	Region 2: Memory at b0200000 (64-bit, non-prefetchable) 
	Region 4: Memory at a8000000 (64-bit, non-prefetchable) 
	Capabilities: <access denied>

I know it has got 130MB non-prefetchable memory, but I need to know if it is possible to avoid BAR2(Region 4) which has got a size 128MB?
When I try to insmod my driver (which is working fine on x86), it is giving a “Segmentation fault (core dumped)”. The error trace back to pci_request_regions() returning 0, but mapping_bars fails.
I’m not even getting anything about any BAR (pci_resource_start,end,length-> all returns 0), even for the BAR0 and BAR1.
Is there anything I can do to solve this?

I also tried pci_request_region(), instead of pci_request_regions() for BAR0 and BAR1.
But that also gives the same Segmentation fault.

Is this the only device connected to Jetson board? If so, you can make modifications to the device-tree to allocate more aperture for mapping non-prefetchable regions of endpoint

--- a/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi
+++ b/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi
@@ -1518,8 +1518,8 @@
                          0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
                          0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
                          0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
-                         0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
-                         0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
+                         0x82000000 0 0x50100000 0x0 0x50100000 0 0x1ff00000   /* non-prefetchable memory (512 MiB) */
+                         0xc2000000 0 0x70000000 0x0 0x70000000 0 0x10000000>; /* prefetchable memory (256 MiB) */

                status = "disabled";

Thanks @vidyas. The problem got solved. :D

Great…
Thanks for the quick verification and update