According to Jetson_AGX_Orin_Series_Design_Guide, PCIe C0 is x1 link. There is no PCIe C6/C8/C9/C10 supported on Jetson_AGX_Orin module. Only one of the two supported configurations can be used in a design. Please see capture shown below for UPHY mapping of USB3.2, PCIE, and MGBE as well as Jetson AGX Orin Pin Names. A design should match or be a subset of Configuration #1 or Configuration #2.
“Orin Series System-on-Chip Technical Reference Manual”, this document seems to be different from what you said.We can see the figure on page 5763,it shows pcie c0 x4.This document also show us the c6/c8/c9/c10. These pcies also apear in the tegra234-soc-pcie.dtsi.For example:
/* C6 X4 */
pcie_c6_ep: pcie_ep@141c0000{
Orin SoC can be designed to virous platforms such as Automotive products , Embedded system, Jetson AGX module developr kit… etc. And there are three UPHY instances (HSIO UPHY 8-lane, NVHS UPHY 8-lane, GBE UPHY 8-lane, total 24 UPHY lane) to support various combinations for PCIe, XUSB, UFS, MGBE use cases.
In “Orin Series System-on-Chip Technical Reference Manual” you pointed out that lists all PCIe controllers in those three UPHY instances. However, since we are discussing about Jetson AGX Orin module developer kit here, that only allows two UPHY configurations as above table shown by board design.