PCIe C5 x8 Link Speed Check

[liyutai]

Hi NV Support Team
Which register can indicate PCIe Link Status / Speed.
Does this is correct reigister: PCIE_X8_RC_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_0

page 6034 from TRM.
PCIE_X8_RC_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_0

Thanks
Yutai

[WayneWWW]

lspci command shall already tell you the link speed. No need to use register dump to check.

[enlaihe]

Hi liyutai:

have you test RC EP PCIe communication?

[liyutai]

Hi Wayne
I use ispici get the below log:
LnkSta: Speed 16GT/s (ok), Width x8 (ok)

That means PCIe working in PCIe 4 mode 16GT/s, Correct?

Thanks
Yutai

[liyutai]

Yes, I have test it . it work well

[enlaihe]

hi liyutai:
below is my step:
1.in p3701.conf.common
ODMDATA=“gbe-uphy-config-22,nvhs-uphy-config-0,hsio-uphy-config-0,gbe0-enable-10g,hsstp-lane-map-3”; to ODMDATA=“gbe-uphy-config-22,nvhs-uphy-config-1,hsio-uphy-config-0,gbe0-enable-10g,hsstp-lane-map-3”
2.# sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1
3.use this patch for ep:

diff --git a/kernel/kernel-5.10/drivers/pci/controller/dwc/pcie-tegra194.c b/kernel/kernel-5.10/drivers/pci/controller/dwc/pcie-tegra194.c
index 7fde1a4d6..981bbac02 100644
--- a/kernel/kernel-5.10/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/kernel/kernel-5.10/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2164,7 +2164,9 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
val |= APPL_INTR_EN_L1_8_INTX_EN;
val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
+#if 0
val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
+#endif
if (IS_ENABLED(CONFIG_PCIEAER))
val |= APPL_INTR_EN_L1_8_AER_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
@@ -3569,9 +3571,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);

+#if 0
val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
+#endif

if (pcie->enable_cdm_check) {
val = appl_readl(pcie, APPL_INTR_EN_L0_0);
@@ -3880,6 +3884,7 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
return &tegra_pcie_epc_features;
}

+#if 0
/* Reserve BAR0_BASE + BAR0_MSI_OFFSET of size SZ_64K as MSI page */
static int tegra_pcie_ep_set_bar(struct dw_pcie_ep *ep, u8 func_no,
                                 struct pci_epf_bar *epf_bar)
@@ -3903,11 +3908,11 @@ static int tegra_pcie_ep_set_bar(struct dw_pcie_ep *ep, u8 func_no,

return 0;
}
+#endif

static struct dw_pcie_ep_ops pcie_ep_ops = {
.raise_irq = tegra_pcie_ep_raise_irq,
.get_features = tegra_pcie_ep_get_features,
-       .set_bar = tegra_pcie_ep_set_bar,
};

static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,

4.start ep exec

# cd /sys/kernel/config/pci_ep/
# mkdir functions/pci_epf_tvnet/func1
# echo 16 > functions/pci_epf_tvnet/func1/msi_interrupts
# ln -s functions/pci_epf_tvnet/func1 controllers/141a0000.pcie_ep/
# echo 1 > controllers/141a0000.pcie_ep/start

5 start rc
and lspci see device id0x2296.
On the endpoint device: ifconfig eth1 up
On the root port system: ifconfig eth1 up
On the endpoint device: ifconfig eth1 192.168.2.1
On the root port system: ifconfig eth1 192.168.2.2

6. ping but fail

Enabling Orin Dev Kit Ethernet over PCIe but ping fail

Hi nvidia team: Following Bringing up an Ethernet Interface over PCIe and using tvnet in order to check bulk transfer between Orin EP and Orin RP, RC command line exec lspci: [图片] now the RC and EP both have eth1. then set On the endpoint device: ifconfig eth1 up On the root port system: ifconfig eth1 up On the endpoint device: ifconfig eth1 192.168.2.1 On the root port system: ifconfig eth1 192.168.2.2 when set EP ifconfig eth1 up met some err. [图片] and EP ping RC fail [图片] he…

do you have any suggest,thanks

[liyutai]

Hi
I need forward your step to our SW colleague to check.

Thanks
Yutai