Hello,
I have a few questions:
I want to connect NVIDIA Jetson Xavier, P/N: 900-82888-0000-000 to:
Thank you,
hello efio,
3. MIPI CSI2 X 4 lanes, MIPI CSI2 X 2 lanes to camera using external connector – Can I connect the lines directly to MIPI camera?
please share more details, may I know what’s the “external connector” you would like to used?
tegra device still recognize it as MIPI camera sensor if you connect it with J509.
4. Do you have Orcad symbol?
please download Jetson AGX Xavier Developer Kit Carrier Board Design Files for reference.
Hi,
Thank you,
Waiting for questions 1-2 to be answered :)
Hi, for 1 & 2, are you testing on devkit or your own carrier board? x8 and x4 are routed to connectors as you can see in reference schematic, you can use them directly if the devices are also with standard PCIe IOs.
Hi,
Just to make sure, can someone write the electrical protocol (voltage levels) of the PCIe?
It’s very important - as you wrote the devkit PCIe outputs connected to external connector so I can’t figure out the voltage levels.
Thank you,
PCIe is 1.8v IO voltage.
Hi,
I saw that, but what is the protocol?
please see the following article:
Refclk Frequency and Jitter Requirements
The industry-standard reference clock frequency used for devices supporting PCIe 1.1, 2.1 and
3.0 is 100 MHz (±300 ppm generated using an HCSL signal format). It is common for embedded
processors, system controllers and SoC-based designs to use 100 MHz HCSL format as the
reference clock for the PCIe bus interface circuitry.
However, in applications that use FPGAs, the PCIe reference clock requirements can deviate
from the standard 100 MHz HCSL format to other frequencies and formats such as 125 MHz, 200
MHz or 250 MHz in LVCMOS, LVDS or LVPECL. A typical example is an FPGA that supports
both PCIe and Ethernet functions. Using a common reference clock frequency of 125 MHz to
clock both functions helps to reduce clocking domains or timing islands in the FPGA. Internally
the FPGA multiplies this reference to the required PCIe lane rate (e.g. 125 MHz x64 for PCIe
3.0). Depending on the mix of ICs used in a design, the PCIe clock strategy may vary from one of
generating multiple 100 MHz HCSL clocks to generating a mix of different frequencies and output
formats.
Sorry, i’m not so clear about your question. If you are asking for the spec of standard of PCIe port, it is indicated in module datasheet, on Xavier, it is PCI Express® Base Specification Revision 4.0, Version 0.7. The external device, including FPGA, can work well if it follow same spec too.
Hi,
Looking into the DG figure 22. I saw that for the X 8 connection (Xavier is root) PEX_CLK5 is routed? can I use other clock? do I need to enable the clock?
For the X 4 connection to NVMe, which lanes and clock should I use (Xavier is root)?
Thank you,
Efi
Hi,
Any answers?
Thank you
Please just follow the design guide to do custom design. We can not support design out of that.